; ================================================== ; RVP8/IFD IF-Digitizer Board Rev.G ; ================================================== ; Common Part and Connector Definitions ; #include "../include/parts.wrp" ; ************** ; * * ; * Change LOG * ; * * ; ************** ; Rewire CLKIN directly to PLL for better stability ; Change R16 to 62-Ohm ; Add C73 0.01uF cap at U9 PLL ; Add C62 0.01uF cap at U10 XTAL ; Add BY119 0.1uF at U2 ; Add BY318 0.01uF at U16 ; Change R71 33->62, R72 130->271 ; Better bypassing around U15 MAX913 to reduce BURST interference ; Add BY310 0.01uF ; Remove traces to old LED pads, but keep the pads themselves. Move ; LED traces away from IF-2 input signals ; Move four switch-->FPGA traces away from IF-2 input signals ; Extend layer 4/5 GND area to include clock transformer ; Straighten etch on POTGAIN, T5 ; Move T3 noise outputs to bottom layer, and route between A/Ds ; Put additional 0.01uF bypass caps on +3.3V and +5V inductors ; Add BY311-BY317 for +5V ; Add BY128-BY130 for +3.3V ; Add R35 to data output of U2. ; ---------------------------------------- ; Test for IF-2 interference from uplink receiver ; Test AUXCLK signals for interference/quality ; ************************* ; * * ; * Altera Stratix FPGA * ; * * ; ************************* $DEF U1 EP1S10F484 ; Global clocks ; $DIP U1 L22 GND L21 CLK0LB ; CLK0n/CLK0p $DIP U1 M22 GND M21 CLK2LB ; CLK2n/CLK2p $DIP U1 M1 GND M2 GND ; CLK9n/CLK9p $DIP U1 L1 GND L2 GND ; CLK11n/CLK11p $DIP U1 L20 GND ; CLK1p $DIP U1 M20 GND ; CLK3p $DIP U1 AA14 GND ; CLK4p (was CLKIN) $DIP U1 V13 GND ; CLK5p $DIP U1 AB11 AUXCLKRX ; CLK6p $DIP U1 AA11 GND ; CLK7p $DIP U1 M3 GND ; CLK8p $DIP U1 L3 GND ; CLK10p $DIP U1 A11 AQCLK2 ; CLK12p $DIP U1 B11 GND ; CLK13p $DIP U1 B14 AQCLK ; CLK14p $DIP U1 E13 GND ; CLK15p $DIP U1 K20 CLK0LB L17 CLK2LB ; Digital Grounds ; $DIP U1 A14 GND A2 GND A21 GND A9 GND AA1 GND AA22 GND $DIP U1 AB14 GND AB2 GND AB21 GND AB9 GND B1 GND B22 GND $DIP U1 G15 GND G17 GND G6 GND J1 GND J22 GND $DIP U1 K11 GND L10 GND L12 GND L14 GND M11 GND M13 GND $DIP U1 M9 GND N12 GND P1 GND P22 GND T17 GND T6 GND $DIP U1 R5 GND H16 GND H9 GND R14 GND ; (For vertical migration to EP1S20) ; VCCINT ; $DIP U1 A1 +1.5V A22 +1.5V AB1 +1.5V AB22 +1.5V K12 +1.5V $DIP U1 L11 +1.5V L13 +1.5V L9 +1.5V M10 +1.5V M12 +1.5V $DIP U1 M14 +1.5V N11 +1.5V ; VCCIO ; $DIP U1 N22 +3.3V Y22 +3.3V C22 +3.3V K22 +3.3V A13 +3.3V $DIP U1 A20 +3.3V A10 +3.3V A3 +3.3V C1 +3.3V K1 +3.3V $DIP U1 N1 +3.3V Y1 +3.3V AB10 +3.3V AB3 +3.3V AB13 +3.3V $DIP U1 AB20 +3.3V ; VREF (for voltage-referenced I/O, unused, so just ground them all) ; $DIP U1 P18 GND H18 GND H14 GND H6 GND J5 GND $DIP U1 R6 GND R9 GND R18 GND R17 GND J18 GND $DIP U1 H15 GND H7 GND H5 GND P5 GND R7 GND $DIP U1 R16 GND ; PLL Analog Grounds and Power. PLLs #5 and #6 also have power for ; dedicated output pins. ; $DIP U1 L19 GND M19 GND M4 GND L4 GND $DIP U1 L18 GND N19 GND N4 GND L5 GND $DIP U1 F12 GND G11 GND U12 GND T11 GND $DIP U1 K19 VCCPLL1 K18 VCCPLL1 ; PLL1 $DIP U1 M18 VCCPLL2 N18 VCCPLL2 ; PLL2 $DIP U1 M5 VCCPLL3 N5 VCCPLL3 ; PLL3 $DIP U1 K4 VCCPLL4 K5 VCCPLL4 ; PLL4 $DIP U1 G13 VCCPLL5 F11 VCCPLL5 ; PLL5 $DIP U1 T12 VCCPLL6 U11 VCCPLL6 ; PLL6 #define PLLBYPASS( NUM, ABC ) \ $DEF C29##ABC CAP0805 0.1uf $DIP C29##ABC 1 VCCPLL##NUM 2 GND \ $DEF C30##ABC CAP0805 0.01uf $DIP C30##ABC 1 VCCPLL##NUM 2 GND \ $DEF FB5##ABC FBEAD1206 $DIP FB5##ABC 1 VCCPLL##NUM 2 +1.5V PLLBYPASS( 1, A ) PLLBYPASS( 3, C ) PLLBYPASS( 5, E ) PLLBYPASS( 2, B ) PLLBYPASS( 4, D ) PLLBYPASS( 6, F ) $DIP U1 F13 +3.3V U13 +3.3V ; VCC_PLL5_OUTA & VCC_PLL6_OUTA $DIP U1 C12 * D12 * ; PLL5_FBn/PLL5_FBp $DIP U1 B13 * C13 * ; PLL5_OUT0n/PLL5_OUT0p $DIP U1 A12 * B12 * ; PLL5_OUT1n/PLL5_OUT1p $DIP U1 Y12 * W12 * ; PLL6_FBn/PLL6_FBp $DIP U1 Y13 * AA13 * ; PLL6_OUT0n/PLL6_OUT0p $DIP U1 AB12 * AA12 * ; PLL6_OUT1n/PLL6_OUT1p ; Configuration pins ; $DIP U1 R10 GND ; VCCSEL, Use 2.5V/3.3V config levels $DIP U1 U10 +3.3V ; PORSEL, 12ms power up (must be < EPC4) $DIP U1 R13 +3.3V ; PLL_ENA, Enable internal PLLs $DIP U1 T13 GND P12 MSEL1 R12 GND ; MSEL0/1/2, select serial configuration $DIP U1 N9 GND ; nIO_PULLUP, weak pullups enabled $DIP U1 L16 * ; CLKUSR, unused $DIP U1 P9 * ; RUnLU, unused $DIP U1 R11 GND P11 * ; nCE, nCEO $DIP U1 J13 CF_DCLK ; DCLK $DIP U1 K13 CF_CONF_DONE ; CONF_DONE $DIP U1 P10 CF_INIT_DONE ; INIT_DONE $DIP U1 H13 CF_NCONFIG ; nCONFIG $DIP U1 J12 CF_NSTATUS ; nSTATUS $DIP U1 L8 CF_D0 J9 CF_D1 H10 CF_D2 K10 CF_D3 ; DATA[0..3] $DIP U1 K14 CF_D4 G14 CF_D5 K15 CF_D6 J15 CF_D7 ; DATA[4..7] $DIP U1 N10 * M8 * R15 * ; PGM0/1/2 $DIP U1 J2 _CF_IO0 K2 _CF_IO1 J3 _CF_IO2 K3 _CF_IO3 $DIP U1 V1 _ISP_ENAB_ T1 _ISP_TCK U2 _ISP_TDI G3 _ISP_TDO U1 _ISP_TMS ; A/D Converters and Noise Generator ; $DIP U1 D19 _ADA0 E20 _ADA1 F21 _ADA2 H21 _ADA3 J21 _ADA4 M16 _ADA5 M17 _ADA6 $DIP U1 P20 _ADA7 N20 _ADA8 P19 _ADA9 N17 _ADA10 K21 _ADA11 J20 _ADA12 H20 _ADA13 $DIP U1 B15 _ADB0 A16 _ADB1 A17 _ADB2 E19 _ADB3 B20 _ADB4 B21 _ADB5 C21 _ADB6 $DIP U1 C9 _ADB7 C8 _ADB8 B8 _ADB9 A8 _ADB10 A7 _ADB11 B6 _ADB12 A6 _ADB13 $DIP U1 F2 _ADC0 F1 _ADC1 F3 _ADC2 H2 _ADC3 H1 _ADC4 G2 _ADC5 G1 _ADC6 $DIP U1 E2 _ADC7 D1 _ADC8 D2 _ADC9 D3 _ADC10 B2 _ADC11 C3 _ADC12 B3 _ADC13 $DIP U1 C18 _ADOVRA C14 _ADOVRB E1 _ADOVRC $DIP U1 H22 GND A5 GND B4 GND ; Was _ADRDYA/B/C $DIP U1 A4 _NGEN0 C4 _NGEN1 D4 _NGEN2 D5 _NGEN3 F4 _NGEN4 ; Auxiliary I/O clocks and outputs ; $DIP U1 M6 _AUXCLKDE T4 _AUXCLKTX $DIP U1 G21 _DAFC ; Downlink Hotlink-I Transmitters and Uplink ; $DIP U1 N8 _BISTENA_ U22 _BISTENB_ Y15 _BISTENC_ $DIP U1 Y8 _FOTOA AB18 _FOTOB AB5 _FOTOC $DIP U1 W5 _TXCLKA AA17 _TXCLKB V4 _TXCLKC $DIP U1 Y7 _TXENABLA_ AA16 _TXENABLB_ W4 _TXENABLC_ $DIP U1 R19 GND A15 GND R20 GND ; Was _TXRPA/B/C_ $DIP U1 AB19 _TXSCA AA18 _TXSCB V3 _TXSCC $DIP U1 N7 _TXSVSA T20 _TXSVSB W14 _TXSVSC $DIP U1 P21 _TXDA0 R21 _TXDA1 R22 _TXDA2 U19 _TXDA3 $DIP U1 W21 _TXDA4 Y21 _TXDA5 Y20 _TXDA6 Y6 _TXDA7 $DIP U1 AA21 _TXDB0 W22 _TXDB1 V21 _TXDB2 V22 _TXDB3 $DIP U1 U20 _TXDB4 U21 _TXDB5 T22 _TXDB6 T21 _TXDB7 $DIP U1 AA6 _TXDC0 AB7 _TXDC1 AB8 _TXDC2 Y9 _TXDC3 $DIP U1 W9 _TXDC4 U9 _TXDC5 W13 _TXDC6 Y14 _TXDC7 $DIP U1 N21 _TXUP ; AFC Analog Output ; $DIP U1 Y5 _DACCLK Y4 _DACDATA AB6 _DACENAB ; Test points, Switches and LEDs ; $DIP U1 D22 _IOT001 E22 _IOT002 F22 _IOT003 G22 _IOT004 $DIP U1 V5 _TPOINTA V9 _TPOINTB $DIP U1 D21 _SW1X_ E21 _SW1Y_ G19 _SW2X_ G20 _SW2Y_ $DIP U1 A18 _LEDG_ A19 _LEDR_ $DIP U1 T3 _RJGRN_ AA20 _RJYEL AA19 _RJYEL_ ; Aquisition Clock ; $DIP U1 W1 _PLL_CLK W3 _PLL_DATA Y2 _PLL_LE Y3 _PLL_LOCK V2 * ; (was _PLL_OSC) $DIP U1 B17 _VCXOSEL ; Temperature monitor ; $DIP U1 AA4 _TEMPALERT AA5 _TEMPCLK AB4 _TEMPDATA AA3 _TEMPOVER ; Remaining general purpose I/O pins ; $DIP U1 G7 _IO1 G9 _IO2 J14 _IO3 J7 _IO4 K7 _IO5 N13 _IO7 N14 _IO8 $DIP U1 N16 _IO9 P7 _IO11 R8 _IO12 T7 _IO13 D13 _IO15 J17 _IO24 R2 _IO41 $DIP U1 R1 _IO42 T2 _IO43 W2 _IO50 K17 _IO68 H19 _IO70 $DIP U1 H17 _IO71 J19 _IO72 G18 _IO75 T18 _IO76 F18 _IO77 F5 _IO82 G5 _IO83 $DIP U1 G4 _IO85 J6 _IO86 J4 _IO87 H3 _IO88 H4 _IO89 K6 _IO90 U18 _IO91 $DIP U1 L6 _IO92 N3 _IO97 N2 _IO98 P3 _IO99 P2 _IO100 N6 _IO102 R3 _IO103 $DIP U1 R4 _IO104 P4 _IO105 P6 _IO106 U5 _IO110 T5 _IO111 P17 _IO114 T19 _IO115 $DIP U1 W6 _IO143 C5 _IO147 B5 _IO149 C6 _IO150 E5 _IO151 D6 _IO152 V7 _IO156 $DIP U1 U7 _IO157 V6 _IO159 U6 _IO161 W7 _IO162 B7 _IO163 E6 _IO164 F7 _IO165 $DIP U1 D7 _IO167 C7 _IO168 F6 _IO169 E7 _IO170 U8 _IO171 V8 _IO172 AA8 _IO178 $DIP U1 E8 _IO179 F8 _IO181 D9 _IO184 E9 _IO185 F9 _IO186 V14 _IO187 U14 _IO189 $DIP U1 U15 _IO190 V15 _IO191 AB15 _IO192 AA15 _IO193 C15 _IO196 D14 _IO197 E14 _IO198 $DIP U1 D15 _IO199 E15 _IO200 F15 _IO201 AB16 _IO203 W16 _IO204 T16 _IO205 Y16 _IO206 $DIP U1 V16 _IO207 V17 _IO208 U16 _IO209 U17 _IO210 E16 _IO212 G16 _IO213 C16 _IO214 $DIP U1 D16 _IO215 F16 _IO216 E17 _IO217 F17 _IO218 AB17 _IO219 Y17 _IO220 W17 _IO221 $DIP U1 V18 _IO222 W18 _IO226 C17 _IO229 D17 _IO230 E18 _IO231 B18 _IO233 D18 _IO234 $DIP U1 Y19 _IO237 W19 _IO241 W20 _IO242 B19 _IO244 C19 _IO245 C20 _IO249 D20 _IO250 $DIP U1 AA2 _IO251 C2 _IO252 AA7 _IO255 W8 _IO257 D8 _IO258 W15 _IO259 F14 _IO260 $DIP U1 B16 _IO262 Y18 _IO263 K16 _IO267 J16 _IO268 T15 _IO269 P16 _IO270 M7 _IO271 $DIP U1 T8 _IO272 G8 _IO273 H8 _IO274 L15 _IO275 K8 _IO276 T9 _IO277 P15 _IO278 $DIP U1 M15 _IO279 J8 _IO280 N15 _IO282 ; No Connect pins ; $DIP U1 AA10 * AA9 * B10 * B9 * C10 * C11 * $DIP U1 D10 * D11 * E10 * E11 * E12 * E3 * $DIP U1 E4 * F19 * F20 * $DIP U1 U3 * U4 * V10 * V11 * V12 * $DIP U1 V19 * V20 * W10 * W11 * Y10 * Y11 * ; Miscellaneous ; $DIP U1 H12 TEMPDIODEN G12 TEMPDIODEP ; Temperature Diode $DIP U1 L7 * ; DEV_OE $DIP U1 P8 * ; DEV_CLRn $DIP U1 P13 * ; CS $DIP U1 P14 * ; RDYnBSY $DIP U1 T14 * ; nCS $DIP U1 T10 * ; nRS $DIP U1 F10 * ; nWS ; ********************************** ; * * ; * Configuration and JTAG Support * ; * * ; ********************************** ; ------------------------------ ; Altera 4/8/16MBit Configuration Device ; $DEF U6 EPC16QC100 $DIP U6 ; Power, GND, and NC 2 GND 41 GND 58 GND 70 GND 69 GND 79 GND 12 +3.3V 22 +3.3V 59 +3.3V 67 +3.3V 68 +3.3V 92 +3.3V 43 +3.3V 3 * 4 * 18 * 19 * 20 * 30 * 63 * 64 * 76 * 77 * 7 * 24 * 57 * 74 * $DIP U6 ; Active configuration pins 11 CF_DCLK 23 CF_NSTATUS 60 CF_CONF_DONE 73 CF_D0 84 CF_D1 88 CF_D2 91 CF_D3 96 CF_D4 10 CF_D5 9 CF_D6 8 CF_D7 14 CF_PGM0 13 CF_PGM1 15 CF_PGM2 16 CF_INIT_CONF $DIP U6 ; Unused flash interface 45 +3.3V ; WP# 55 * 54 * 53 * 52 * 51 * 50 * 34 * 32 * 31 * 29 * 28 * 27 * 26 * 49 * 47 * 46 * 36 * 81 * 83 * 86 * 89 * 93 * 95 * 98 * 100 * 82 * 85 * 87 * 90 * 94 * 97 * 99 * 1 * 37 * 80 * 78 * $SW U6 39 U6 72 ; F-RP# <-> C-RP# $SW U6 33 U6 38 ; F-WE# <-> C-WE# $SW U6 75 U6 65 ; F-A0 <-> C-A0 $SW U6 56 U6 62 ; F-A1 <-> C-A1 $SW U6 25 U6 21 ; F-A15 <-> C-A15 $SW U6 6 U6 17 ; F-A16 <-> C-A16 $DIP U6 ; Other pins 40 +3.3V 71 GND ; TM1, TM0 66 GND ; PORSEL (100 ms) 5 +3.3V ; BYTE# 61 GND ; EXCLK ; Support functions provided by a small 7000 series FPGA. This ; handles the latching of PGM[2:0] pins, strobing of nCONFIG, ; board serial number, board version, etc. ; $DEF U7 EPM7064AETC44 $DIP U7 16 GND 36 GND 4 GND 24 GND 17 +3.3V 41 +3.3V 9 +3.3V 29 +3.3V 37 AQCLK 40 AQCLK2 39 GND 38 GND 2 CF_NCONFIG 3 CF_INIT_DONE 5 * 6 _CF_IO0 8 _CF_IO1 10 _CF_IO2 11 _CF_IO3 12 AQCLK2 13 MSEL1 14 * 15 * 18 * 19 * 20 * 21 * 22 * 23 * 25 * 27 * 28 CF_CONF_DONE 30 * 31 CF_JUMP2 33 CF_JUMP1 34 CF_PGM2 35 CF_PGM1 42 CF_PGM0 43 CF_INIT_CONF 44 CF_NSTATUS $DEF N5 RNET_BUS_10 2.2K $DIP N5 5 +3.3V 10 +3.3V $DIP N5 1 CF_NCONFIG 2 CF_CONF_DONE 3 CF_NSTATUS 4 CF_INIT_DONE 6 _CF_IO0 7 _CF_IO1 8 _CF_IO2 9 _CF_IO3 $DEF R36 RES1206 5.1K $DIP R36 1 +3.3V 2 CF_JUMP1 $DEF R37 RES1206 5.1K $DIP R37 1 +3.3V 2 CF_JUMP2 $DEF JP5 JUMP3 $DIP JP5 A CF_JUMP1 B GND C CF_JUMP2 $DEF MSEL1 TPAD_040 $DIP MSEL1 1 MSEL1 ; ------------------------------ ; JTAG Chain. The 1S10 device, 7K device, and Config device are the ; three chips that are wired into the chain. ; ; TDI --> U6 --> U7 --> U1 --> TDO ; $DEF P1 HDSH2X5 ; JTAG header (even side toward board edge) $DIP P1 1 JHDR_TCK 3 JHDR_TDO 5 JHDR_TMS 7 * 9 JHDR_TDI 2 GND 4 +3.3V 6 * 8 * 10 GND ; Signal buffers so that no external signal is directly connected to ; any of the expensive chip pins. ; $DEF U8 74AC244SC $DIP U8 10 GND 20 +3.3V 19 GND 18 JHDR_TCK 16 JHDR_TMS 14 JHDR_TDI 8 JHDR_TDO 17 JHDR_TCK 15 JHDR_TMS 13 JHDR_TDI 9 JHDR_TDO 2 _ISP_TCK 4 _ISP_TMS 6 _ISP_TDI 12 _ISP_TDO 3 JTAG_TCK 5 JTAG_TMS 7 JTAG_TDI 11 JTAG_TDO $DEF N6 RNET_BUS_10 2.2K $DIP N6 5 +3.3V 10 +3.3V $DEF N7 RNET_BUS_10 2.2K $DIP N7 5 GND 10 GND $DIP N6 9 _ISP_TMS 8 _ISP_TDI 7 _ISP_TDO 3 JTAG_TDO 2 JHDR_TDI 1 JHDR_TMS $DIP N7 9 _ISP_TCK 1 JHDR_TCK $DEF JP2 JUMP3 $DIP JP2 A _ISP_ENAB_ C GND $SW JP2 B N6 4 U8 1 ; The JTAG chain itself... ; $DIP U6 42 JTAG_TDI 48 JTAG_TMS 35 JTAG_TCK $DIP U7 7 JTAG_TMS 26 JTAG_TCK $DIP U1 H11 JTAG_TDO G10 JTAG_TMS K9 JTAG_TCK J10 +3.3V $SW U6 44 U7 1 ; U6 TDO --> U7 TDI $SW U7 32 U1 J11 ; U7 TDO --> U1 TDI ; ******************** ; * * ; * A/D Converters * ; * * ; ******************** ; Fundamental A/D converter is identical for all three input channels. ; First define the chip itself, plus analog and digital power ; supplies. ; #define ADCONVERT( ABC ) \ $DEF U5##ABC AD6645ASQ \ $DIP U5##ABC 8 AVCC##ABC 9 AVCC##ABC 14 AVCC##ABC 16 AVCC##ABC 18 AVCC##ABC \ $DIP U5##ABC 22 AVCC##ABC 26 AVCC##ABC 28 AVCC##ABC 30 AVCC##ABC \ $DIP U5##ABC 1 DVCC##ABC 33 DVCC##ABC 43 DVCC##ABC 3 VREF##ABC 31 * 35 * \ $DIP U5##ABC 2 GND 4 GND 7 GND 10 GND 13 GND 15 GND 17 GND 19 GND \ $DIP U5##ABC 21 GND 23 GND 25 GND 27 GND 29 GND 34 GND 42 GND 52 * \ \ $DEF L3##ABC IND_AXIL_040 1.5uh $DIP L3##ABC 2 AVCC##ABC 1 +5V \ $DEF C8##ABC CAP1206 4.7uf $DIP C8##ABC 1 AVCC##ABC 2 GND \ $DEF C9##ABC CAP0805 0.1uf $DIP C9##ABC 1 AVCC##ABC 2 GND \ $DEF C10##ABC CAP0805 0.1uf $DIP C10##ABC 1 AVCC##ABC 2 GND \ $DEF C11##ABC CAP0805 0.1uf $DIP C11##ABC 1 AVCC##ABC 2 GND \ $DEF C12##ABC CAP0805 0.1uf $DIP C12##ABC 1 AVCC##ABC 2 GND \ $DEF C13##ABC CAP0805 0.01uf $DIP C13##ABC 1 AVCC##ABC 2 GND \ $DEF C14##ABC CAP0805 0.01uf $DIP C14##ABC 1 AVCC##ABC 2 GND \ $DEF C15##ABC CAP0805 0.01uf $DIP C15##ABC 1 AVCC##ABC 2 GND \ \ $DEF L4##ABC IND_AXIL_040 1.5uh $DIP L4##ABC 2 DVCC##ABC 1 +3.3V \ $DEF C18##ABC CAP1206 4.7uf $DIP C18##ABC 1 DVCC##ABC 2 GND \ $DEF C19##ABC CAP0805 0.1uf $DIP C19##ABC 1 DVCC##ABC 2 GND \ $DEF C20##ABC CAP0805 0.01uf $DIP C20##ABC 1 DVCC##ABC 2 GND \ \ $DEF C16##ABC CAP0805 0.1uf $DIP C16##ABC 2 GND $SW C16##ABC 1 U5##ABC 20 \ $DEF C17##ABC CAP0805 0.1uf $DIP C17##ABC 2 GND $SW C17##ABC 1 U5##ABC 24 \ $DEF C25##ABC CAP0805 0.1uf $DIP C25##ABC 2 GND 1 VREF##ABC ; Clock and Video inputs ; #define ADCINPUTS( ABC ) \ $DEF T1##ABC XFMR_TTMO 4:1 $DIP T1##ABC 7 GND 8 GND 6 GND 4 * \ $DEF C22##ABC CAP0805 0.1uf $DIP C22##ABC 1 ADCLK##ABC \ $DEF C21##ABC CAP0805 0.1uf $DIP C21##ABC 2 GND \ $DEF R17##ABC RES1206 25 \ $DEF R18##ABC RES1206 25 \ $DEF D2##ABC HSMS2812 \ $SW C22##ABC 2 T1##ABC 2 \ $SW C21##ABC 1 T1##ABC 3 \ $SW R17##ABC 1 T1##ABC 1 \ $SW R18##ABC 1 T1##ABC 5 \ $SW R17##ABC 2 U5##ABC 5 D2##ABC 3 \ $SW R18##ABC 2 U5##ABC 6 D2##ABC 1 D2##ABC 2 \ \ $DEF T2##ABC XFMR_TTMO 4:1 $DIP T2##ABC 7 GND 8 GND 5 NOISE##ABC \ $DEF C23##ABC CAP0805 0.1uf $DIP C23##ABC 1 IFIN##ABC \ $DEF C24##ABC CAP0805 0.1uf $DIP C24##ABC 2 GND \ $DEF R19##ABC RES1206 25 \ $DEF R20##ABC RES1206 25 \ $DEF R21##ABC RES1206 649 \ $DEF R22##ABC RES1206 25 $DIP R22##ABC 2 GND \ $SW C23##ABC 2 T2##ABC 1 \ $SW C24##ABC 1 T2##ABC 4 \ $SW R22##ABC 1 T2##ABC 3 \ $SW R19##ABC 1 R21##ABC 1 T2##ABC 2 \ $SW R20##ABC 1 R21##ABC 2 T2##ABC 6 \ $SW R19##ABC 2 U5##ABC 11 \ $SW R20##ABC 2 U5##ABC 12 ; Digital outputs and damping resistors ; #define ADCOUTPUTS( ABC ) \ $DEF N1##ABC RNET_ISO_08 390 $DEF N3##ABC RNET_ISO_08 390 \ $DEF N2##ABC RNET_ISO_08 390 $DEF N4##ABC RNET_ISO_08 390 \ \ $DIP N1##ABC 8 * 1 * 7 _AD##ABC##13 6 _AD##ABC##12 5 _AD##ABC##11 \ $DIP N2##ABC 8 _AD##ABC##10 7 _AD##ABC##9 6 _AD##ABC##8 5 _AD##ABC##7 \ $DIP N3##ABC 8 _AD##ABC##6 7 _AD##ABC##5 6 _AD##ABC##4 5 _AD##ABC##3 \ $DIP N4##ABC 8 _AD##ABC##2 7 _AD##ABC##1 6 _AD##ABC##0 5 _ADOVR##ABC \ \ $SW U5##ABC 44 N3##ABC 1 \ $SW U5##ABC 51 N1##ABC 2 $SW U5##ABC 41 N3##ABC 2 \ $SW U5##ABC 50 N1##ABC 3 $SW U5##ABC 40 N3##ABC 3 \ $SW U5##ABC 49 N1##ABC 4 $SW U5##ABC 39 N3##ABC 4 \ $SW U5##ABC 48 N2##ABC 1 $SW U5##ABC 38 N4##ABC 1 \ $SW U5##ABC 47 N2##ABC 2 $SW U5##ABC 37 N4##ABC 2 \ $SW U5##ABC 46 N2##ABC 3 $SW U5##ABC 36 N4##ABC 3 \ $SW U5##ABC 45 N2##ABC 4 $SW U5##ABC 32 N4##ABC 4 ; Now build them all... ; ADCONVERT( A ) ADCONVERT( B ) ADCONVERT( C ) ADCINPUTS( A ) ADCINPUTS( B ) ADCINPUTS( C ) ADCOUTPUTS( A ) ADCOUTPUTS( B ) ADCOUTPUTS( C ) ; The 'A' and 'B' channels are IF-1 and IF-2. These both have an ; additive noise source that is coupled in via the input transformer. ; The 'C' channel BURST input does not need a noise source since the ; signal levels are large. ; #define NOISEFILTER( AB ) \ $DEF R31##AB RES1206 130 $DIP R31##AB 2 GND \ $DEF R32##AB RES1206 130 $DIP R32##AB 2 NOISE##AB \ \ $DEF C33##AB CAP0805 3300pf $DIP C33##AB 2 GND \ $DEF C34##AB CAP0805 3300pf $DIP C34##AB 2 GND \ $DEF C35##AB CAP0805 3300pf $DIP C35##AB 2 GND \ $DEF C36##AB CAP0805 3300pf $DIP C36##AB 2 GND \ $DEF C37##AB CAP0805 270pf $DIP C37##AB 2 GND \ \ $DEF L10##AB IND1008 1uh $DIP L10##AB 1 NSMID##AB \ $DEF L11##AB IND1210 15uh \ $DEF L12##AB IND1210 15uh \ $DEF L13##AB IND1008 1uh \ \ $SW L10##AB 2 C33##AB 1 L11##AB 1 \ $SW L11##AB 2 C34##AB 1 C35##AB 1 L12##AB 1 \ $SW L12##AB 2 C36##AB 1 L13##AB 1 \ $SW L13##AB 2 C37##AB 1 R31##AB 1 R32##AB 1 NOISEFILTER( A ) NOISEFILTER( B ) $DEF R32C RES1206 62 $DIP R32C 1 GND 2 NOISEC ; Narrow-Band Noise Sources. Common drive section. ; $DEF R23 RES1206 5.1K $DIP R23 1 _NGEN0 $DEF R24 RES1206 649 $DIP R24 1 _NGEN1 $DEF R25 RES1206 271 $DIP R25 1 _NGEN2 $DEF R26 RES1206 271 $DIP R26 1 _NGEN3 $DEF R27 RES1206 130 $DIP R27 1 _NGEN4 $DEF C28 CAP0805 3300pf $DIP C28 2 GND $DEF C29 CAP0805 3300pf $DIP C29 2 GND $DEF C30 CAP0805 3300pf $DIP C30 2 GND $DEF C31 CAP0805 3300pf $DIP C31 2 GND $DEF C32 CAP0805 270pf $DIP C32 2 GND $DEF L6 IND1210 15uh $DEF L7 IND1210 15uh $DEF L8 IND1008 1uh $DEF L9 IND1008 1uh $DEF R29 RES1206 62 $DIP R29 2 GND $DEF R28 RES1206 271 $DEF R30 RES1206 25 $DIP R30 2 GND $DEF T3 XFMR_TTMO 4:1 $DIP T3 4 * 6 GND 7 GND 8 GND 1 NSMIDA 5 NSMIDB $SW R23 2 R24 2 R25 2 R26 2 R27 2 C28 1 L6 1 $SW L6 2 C29 1 C30 1 L7 1 $SW L7 2 C31 1 L8 1 $SW L8 2 C32 1 L9 1 $SW L9 2 R29 1 R28 1 $SW T3 2 R28 2 $SW T3 3 R30 1 ; Attach the SMA input connectors ; $DEF J1A SMA_RT $DIP J1A CENTER IFINA RING1 GND RING2 GND RING3 GND RING4 GND $DEF J1 SMA_RT $DIP J1 CENTER IFINB RING1 GND RING2 GND RING3 GND RING4 GND $DEF J2 SMA_RT $DIP J2 CENTER IFINC RING1 GND RING2 GND RING3 GND RING4 GND ; *************************** ; * * ; * Serial Communications * ; * * ; *************************** ; MagJack signal connections and LEDs. The metal body of the RJ-45 ; connector is floating on the IFD side, but bypassed to AC ground via ; a 1000pf 2KV capacitor. ; $DEF J5 PULSE_JK0_0016 $DIP J5 SH1 RJ45SH SH2 RJ45SH $DEF C71 CAP_CERRAD_030 1000pf $DIP C71 1 GND 2 RJ45SH $DIP J5 2 PTXA+ 7 PTXCTA 3 PTXA- ; Downlink Ch.A $DIP J5 4 PTXB+ 12 PTXCTB 5 PTXB- ; Downlink Ch.B $DIP J5 10 PTXC+ 6 PTXCTC 11 PTXC- ; Downlink Ch.C $DIP J5 9 PRX+ 1 PRXCT 8 PRX- ; Uplink $DIP J5 15 _RJYEL 16 _RJYEL_ 13 _RJGRN_ $DEF R11A RES1206 130 $DIP R11A 1 +3.3V 2 _RJYEL_ $DEF R11B RES1206 130 $DIP R11B 1 +3.3V 2 _RJYEL $DEF R12 RES1206 130 $DIP R12 1 +3.3V $SW R12 2 J5 14 ; Downlink passive equalization (three channels) ; #define TXEQUALIZATION( ABC ) \ $DEF C1##ABC CAP0805 0.1uf $DIP C1##ABC 1 PTXCT##ABC 2 GND \ $DEF R2##ABC RES1206 33 $DIP R2##ABC 1 PTX##ABC##+ 2 TX##ABC##+ \ $DEF R3##ABC RES1206 33 $DIP R3##ABC 1 PTX##ABC##- 2 TX##ABC##- TXEQUALIZATION( A ) TXEQUALIZATION( B ) TXEQUALIZATION( C ) ; Dowlink Hotlink-I transmitters (three channels) ; #define TXHOTLINK( ABC ) \ $DEF U3##ABC CY7B923J \ $DIP U3##ABC 4 HVCC##ABC 9 HVCC##ABC 22 HVCC##ABC 6 GND 20 GND 7 GND \ $DIP U3##ABC 28 HVCC##ABC 1 HVCC##ABC 3 HVCC##ABC 2 HVCC##ABC \ $DIP U3##ABC 27 TX##ABC##+ 26 TX##ABC##- \ $DIP U3##ABC 18 _TXD##ABC##0 17 _TXD##ABC##1 16 _TXD##ABC##2 15 _TXD##ABC##3 \ $DIP U3##ABC 14 _TXD##ABC##4 13 _TXD##ABC##5 12 _TXD##ABC##6 11 _TXD##ABC##7 \ $DIP U3##ABC 19 _TXSC##ABC 10 _TXSVS##ABC 23 _TXENABL##ABC##_ 21 _TXCLK##ABC \ $DIP U3##ABC 25 _FOTO##ABC 5 _BISTEN##ABC##_ 8 * 24 +5TXPULL \ \ $DEF L5##ABC IND_AXIL_040 1.5uh $DIP L5##ABC 1 HVCC##ABC 2 +5V \ $DEF C27##ABC CAP1206 4.7uf $DIP C27##ABC 1 HVCC##ABC 2 GND \ $DEF C26##ABC CAP0805 0.1uf $DIP C26##ABC 1 HVCC##ABC 2 GND \ $DEF C6##ABC CAP0805 0.01uf $DIP C6##ABC 1 HVCC##ABC 2 GND \ $DEF C70##ABC CAP0805 0.01uf $DIP C70##ABC 1 HVCC##ABC 2 GND \ $DEF R13##ABC RES1206 271 $DIP R13##ABC 1 TX##ABC##+ 2 GND \ $DEF R14##ABC RES1206 271 $DIP R14##ABC 1 TX##ABC##- 2 GND TXHOTLINK( A ) TXHOTLINK( B ) TXHOTLINK( C ) $DEF R15 RES1206 5.1K $DIP R15 1 +5V 2 +5TXPULL ; Uplink receiver ; $DEF C2 CAP0805 0.1uf $DIP C2 1 PRXCT 2 GND $DEF L2 IND1812 3.3uh $DIP L2 1 PRX+ $DEF R4 RES1206 180 $DIP R4 1 PRX- $SW L2 2 R4 2 $DEF C3 CAP0805 470pf $DIP C3 1 PRX+ 2 RX+ $DEF C4 CAP0805 470pf $DIP C4 1 PRX- 2 RX- $DEF R5 RES1206 33 $DIP R5 1 PRX+ 2 RX+ $DEF R6 RES1206 33 $DIP R6 1 PRX- 2 RX- $DEF R7 RES1206 2.2K $DIP R7 1 +3.3V 2 RX+ $DEF R8 RES1206 2.2K $DIP R8 1 +3.3V 2 RX- $DEF R9 RES1206 2.2K $DIP R9 1 GND 2 RX+ $DEF R10 RES1206 2.2K $DIP R10 1 GND 2 RX- $DEF U2 SN65LVDT2DBV $DIP U2 3 RX+ 4 RX- 1 +3.3V 2 GND 5 TXUP_DRV $DEF C5 CAP0805 0.01uf $DIP C5 1 +3.3V 2 GND $DEF R35 RES1206 62 $DIP R35 1 TXUP_DRV 2 _TXUP ; *********************************** ; * * ; * Internal VCXO/XO System Clock * ; * * ; *********************************** ; PLL lowpass filter and system clock. This is the master AQ sampling ; clock for all operations within the IFD. It can be either a crystal ; oscillator, or a VCXO. ; $DEF U9 LMX2306TM $DIP U9 13 _PLL_LE 12 _PLL_DATA 11 _PLL_CLK 8 CLKIN 14 _PLL_LOCK 10 PLLVCC 7 PLLVCC 15 PLLVCC 16 PLLVP 2 VCXCP 1 * 3 GND 4 GND 9 GND $DEF R73 RES1206 5.1K $DIP R73 1 +3.3V 2 _PLL_LOCK $DEF C49 CAP0805 0.1uf $DIP C49 2 GND $SW C49 1 U9 5 $DEF C69 CAP0805 0.1uf $SW C69 1 U9 6 $DEF R44 RES1206 649 $DIP R44 1 AQCLKSRC $DEF R70 RES1206 130 $DIP R70 1 GND $SW R44 2 R70 2 C69 2 $DEF C50 TNT1206 15uf $DIP C50 1 PLLVCC 2 GND $DEF C51 CAP0805 0.1uf $DIP C51 1 PLLVCC 2 GND $DEF C73 CAP0805 0.01uf $DIP C73 1 PLLVCC 2 GND $DEF FB2 FBEAD1206 $DIP FB2 1 +3.3V 2 PLLVCC $DEF C52 TNT1206 15uf $DIP C52 1 PLLVP 2 GND $DEF C53 CAP0805 0.1uf $DIP C53 1 PLLVP 2 GND $DEF FB3 FBEAD1206 $DIP FB3 1 +5V 2 PLLVP $DEF R45 RES1206 5.1K $DIP R45 1 VCXCP 2 VCXFB $DEF R46 RES1206 20K $DIP R46 2 GND $DEF C54 CAP1210 10uf $DIP C54 1 VCXCP $SW R46 1 C54 2 $DEF C55 CAP1206 0.47uf $DIP C55 1 VCXCP 2 GND $DEF C56 CAP1210 0.47uf $DIP C56 1 VCXFB 2 GND $DEF TPC TPOINT $DIP TPC 1 VCXFB $DEF U10 CANCLK14 72.0000 $DIP U10 7 GND 8 AQCLKSRC 14 VCXVCC 1 VCXFB $DEF C60 TNT1206 15uf $DIP C60 1 VCXVCC 2 GND $DEF C61 CAP0805 0.1uf $DIP C61 1 VCXVCC 2 GND $DEF C62 CAP0805 0.01uf $DIP C62 1 VCXVCC 2 GND $DEF R65 RES1206 62 $DIP R65 1 AQCLKSRC 2 ADCLKA $DEF R66 RES1206 62 $DIP R66 1 AQCLKSRC 2 ADCLKB $DEF R67 RES1206 62 $DIP R67 1 AQCLKSRC 2 ADCLKC $DEF R47 RES1206 33 $DIP R47 1 AQCLKSRC 2 AQCLK $DEF R68 RES1206 130 $DIP R68 1 GND 2 AQCLK ; Jumper to force the crystal oscillator control pin HIGH. This sets ; either a fixed level for an XO or active feedback for a VCXO, and ; also lets the FPGA monitor which selection has been made. ; $DEF JP4 JUMP3 $DIP JP4 A _VCXOSEL C VCXFB $DEF R48 RES1206 1.2K $DIP R48 1 +5V $DIP N7 2 _VCXOSEL $SW JP4 B R48 2 ; Isolated/Regulated +5V power for VCXO. This is the prefered voltage ; source and should always be used unless the IFD is not provided with ; +12V, in which case a jumper can select the on-board +5V. ; $DEF U11 LP2988AIM 5V $DIP U11 4 +12V 8 +12V 3 GND 5 REG5V 6 REG5V 2 * 7 * $DEF C57 CAP0805 0.1uf $DIP C57 2 GND $SW C57 1 U11 1 $DEF C58 CAP1206 4.7uf $DIP C58 1 +12V 2 GND $DEF C59 CAP1206 4.7uf $DIP C59 1 REG5V 2 GND $DEF L15 IND_AXIL_040 1.5uh $DIP L15 1 INT5V 2 +5V $DEF JP3 JUMP3 $DIP JP3 A REG5V C INT5V $DEF FB4 FBEAD1206 $DIP FB4 1 VCXVCC $SW FB4 2 JP3 B ; ***************************************** ; * * ; * AFC Output and External Clock Input * ; * * ; ***************************************** ; AFC Analog Tuning Voltage ; $DEF U14 AD766JN $DIP U14 8 -12V 2 GND 3 +12V 1 -12V 12 GND 16 +12V 5 _DACCLK 7 _DACDATA 6 _DACENAB 9 VREF- 4 * 10 * 14 * 15 * $DEF U12 AD826AR $DIP U12 8 +12V 4 -12V 3 GND 5 VREFC 7 VREF+ 6 VREF+ $DEF U13 LT1010CN8 $DIP U13 1 +12V 2 * 3 AFCLEV 4 * 5 * 6 -12V 7 * $DEF R49 RES1206 5.1K $DIP R49 1 VREF+ $DEF R50 RES1206 5.1K $DIP R50 2 VREF- $SW R49 2 R50 1 U14 11 $DEF POTGAIN SIPOT_RT 200 $DIP POTGAIN 1 GND $DEF POTOFF SIPOT_RT 5K $DIP POTOFF 1 VREF+ 3 VREF- $DEF R53 RES1206 2.2K $DEF R54 RES1206 5.1K $DEF R55 RES1206 2.2K $DEF R56 RES1206 2.2K $DEF C63 CAP0805 0.1uf $DIP C63 2 GND $SW U14 13 POTGAIN 2A POTGAIN 2B $SW POTGAIN 3 U12 2 R54 1 R53 2 $SW R53 1 POTOFF 2A POTOFF 2B $SW R54 2 U12 1 R55 1 $SW R55 2 C63 1 R56 1 $SW R56 2 U13 8 ; Differential clock receiver ; $DEF T4 XFMR_TTMO 4:1 $DIP T4 3 * 5 GND 7 GND 8 GND 4 T4CT $DEF R57 RES1206 2.2K $DIP R57 1 T4CT 2 +5V $DEF R58 RES1206 2.2K $DIP R58 1 T4CT 2 GND $DEF C64 CAP0805 0.1uf $DIP C64 1 T4CT 2 GND $DEF C65 CAP0805 0.1uf $DEF U15 MAX913CSA $DIP U15 1 +5V 7 CLKIN_DRV 4 GND 5 GND 6 GND 8 * $DEF R16 RES1206 62 $DIP R16 1 CLKIN_DRV 2 CLKIN $SW T4 1 C65 2 $SW T4 2 U15 2 $SW T4 6 U15 3 ; The SMA connector can be jumpered for AFC, and Term/Unterm clock ; input. ; $DEF J3 SMA_RT $DIP J3 RING1 GND RING2 GND RING3 GND RING4 GND $DEF R51 RES1206 25 $DEF R52 RES1206 25 $DEF JP1 JUMP3 $DIP JP1 A AFCLEV C GND $SW R52 2 JP1 B $SW R52 1 R51 2 $SW J3 CENTER R51 1 C65 1 ; ****************************** ; * * ; * DAFC and Auxiliary Clock * ; * * ; ****************************** ; DAFC output is DC-Coupled for legacy 'uplink' devices. The ; signaling level can be either +5V or +12V ; $DEF U17 TC1412NCOA $DIP U17 4 GND 5 GND 3 * 2 _DAFC $DEF JP6 JUMP3 $DEF JP7 JUMP3 $DIP JP7 A +5V C +12V $DEF C68 CAP1206 4.7uf $DIP C68 2 GND $DEF R63 RES1206 25 $DEF R64 RES1206 25 $DEF J4 SMA_RT $DIP J4 RING1 GND RING2 GND RING3 GND RING4 GND $SW U17 1 U17 8 C68 1 JP7 B $SW U17 7 U17 6 R63 2 $SW R63 1 R64 2 $SW JP6 A R64 1 $SW JP6 B J4 CENTER ; The auxiliary clock uses RS-485 signaling that is transformer ; coupled to single-ended coax. Output clocks can be generated, ; and input clocks can be received. ; $DEF U16 MAX3443ECSA $DIP U16 8 +5V 5 GND 2 GND 1 AUXCLKRX_DRV 3 _AUXCLKDE 4 _AUXCLKTX $DEF R71 RES1206 62 $DIP R71 1 AUXCLKRX_DRV 2 AUXCLKRX $DEF R72 RES1206 271 $DIP R72 1 GND 2 AUXCLKRX $DEF T5 XFMR_TTMO 4:1 $DIP T5 3 * 5 GND 7 GND 8 GND 4 T5CT $DEF R59 RES1206 62 $SW T5 2 R59 2 $SW U16 6 R59 1 $DEF R60 RES1206 62 $SW T5 6 R60 2 $SW U16 7 R60 1 $DEF R61 RES1206 2.2K $DIP R61 1 T5CT 2 +5V $DEF R62 RES1206 2.2K $DIP R62 1 T5CT 2 GND $DEF C66 CAP0805 0.1uf $DIP C66 1 T5CT 2 GND $DEF C67 CAP0805 0.1uf $SW C67 2 T5 1 $SW C67 1 JP6 C ; ***************************** ; * * ; * Miscellaneous Circuitry * ; * * ; ***************************** ; ------------------------------ ; Front panel toggle switches ; $DEF R38 RES1206 5.1K $DIP R38 1 +3.3V 2 _SW1X_ $DEF R39 RES1206 5.1K $DIP R39 1 +3.3V 2 _SW1Y_ $DEF SW1 TOGSPDT_RT $DIP SW1 1 _SW1X_ 2 GND 3 _SW1Y_ $DEF R40 RES1206 5.1K $DIP R40 1 +3.3V 2 _SW2X_ $DEF R41 RES1206 5.1K $DIP R41 1 +3.3V 2 _SW2Y_ $DEF SW2 TOGSPDT_RT $DIP SW2 1 _SW2X_ 2 GND 3 _SW2Y_ ; ------------------------------ ; Front panel LEDs ; $DEF LEDG DIALIGHT551_11 GRN $DIP LEDG 1 _LEDG_ $DEF LEDR DIALIGHT551_11 RED $DIP LEDR 1 _LEDR_ $DEF R42 RES1206 130 $DIP R42 1 +3.3V $DEF R43 RES1206 130 $DIP R43 1 +3.3V $SW R42 2 LEDG 2 $SW R43 2 LEDR 2 $DEF TPGRN- TPAD_065 $DEF TPRED- TPAD_065 $DEF TPGRN+ TPAD_065 $DEF TPRED+ TPAD_065 ; ------------------------------ ; Temperature Sense ; $DEF U18 MAX1619MEE $DIP U18 1 TEMPVCC 2 GND 3 TEMPDIODEP 4 TEMPDIODEN 5 * 6 GND 7 GND 8 GND 9 _TEMPOVER 10 GND 11 _TEMPALERT 12 _TEMPDATA 13 * 14 _TEMPCLK 15 TEMPVCC 16 * $DEF R69 RES1206 180 $DIP R69 1 +3.3V 2 TEMPVCC $DEF C72 CAP0805 0.1uf $DIP C72 1 GND 2 TEMPVCC $DEF N8 RNET_BUS_10 2.2K $DIP N8 5 +3.3V 10 +3.3V $DIP N8 1 _TEMPOVER 2 _TEMPALERT 3 _TEMPDATA 4 _TEMPCLK ; ------------------------------ ; Unused fractional parts ; $DIP N6 6 * $DIP N7 3 * 4 * 6 * 7 * 8 * $DIP N8 6 * 7 * 8 * 9 * ; ************************************ ; * * ; * Power Supplies and Mechanicals * ; * * ; ************************************ ; ------------------------------ ; Power entry begins with connections from the terminal block that are ; made to the following solder pads. This is where power enters the ; board. ; $DEF GNDBLK 125PAD_045 $DIP GNDBLK 1 GNDBLK $DEF +5BLK 125PAD_045 $DIP +5BLK 1 +5BLK $DEF +VBLK 125PAD_045 $DIP +VBLK 1 +VBLK $DEF -VBLK 125PAD_045 $DIP -VBLK 1 -VBLK ; First stage capacitors and reverse-voltage protection diodes ; $DEF C38A CAP0805 3300pf $DIP C38A 1 +5BLK 2 GNDBLK $DEF C38B CAP0805 3300pf $DIP C38B 1 +VBLK 2 GNDBLK $DEF C38C CAP0805 3300pf $DIP C38C 1 -VBLK 2 GNDBLK $DEF D3A 1N5818 $DIP D3A 1 +5BLK 2 GNDBLK $DEF D3B 1N5818 $DIP D3B 1 +VBLK 2 GNDBLK $DEF D3C 1N5818 $DIP D3C 2 -VBLK 1 GNDBLK ; Ferrite beads to second stage, w/dual 0.01/0.1 capacitors ; $DEF FB1 FBEAD1206 $DIP FB1 1 GNDBLK 2 GNDMID $DEF FB1A FBEAD1206 $DIP FB1A 1 +5BLK 2 +5MID $DEF FB1B FBEAD1206 $DIP FB1B 1 +VBLK 2 +VMID $DEF FB1C FBEAD1206 $DIP FB1C 1 -VBLK 2 -VMID $DEF C39A CAP0805 0.01uf $DIP C39A 1 +5MID 2 GNDMID $DEF C39B CAP0805 0.01uf $DIP C39B 1 +VMID 2 GNDMID $DEF C39C CAP0805 0.01uf $DIP C39C 1 -VMID 2 GNDMID $DEF C40A CAP0805 0.1uf $DIP C40A 1 +5MID 2 GNDMID $DEF C40B CAP0805 0.1uf $DIP C40B 1 +VMID 2 GNDMID $DEF C40C CAP0805 0.1uf $DIP C40C 1 -VMID 2 GNDMID ; Inductors to third stage, with bulk cap bypass. This generates the ; actual GROUND, +5V and +/-12V internal rails. ; $DEF L14 IND_AXIL_085 33uh $DIP L14 1 GNDMID 2 GND $DEF L14A IND_AXIL_085 33uh $DIP L14A 1 +5MID 2 +5V $DEF L14B IND_AXIL_055 22uh $DIP L14B 1 +VMID 2 +12V $DEF L14C IND_AXIL_055 22uh $DIP L14C 1 -VMID 2 -12V $DEF C41A CAP_VSF 330uf $DIP C41A 1 +5V 2 GND $DEF C41B CAP_VSF 330uf $DIP C41B 1 +12V 2 GND $DEF C41C CAP_VSF 330uf $DIP C41C 2 -12V 1 GND ; ------------------------------ ; 3.3V Series Regulator (PW1) ; $DEF VR1 LP3856ES 3.3V $DIP VR1 1 +5V 2 +5V ; Shutdown, Vin 3 GND 6 GND ; Grounds 4 PW1_VOUT 5 PW1_VOUT ; Vout, Sense $DEF C42 CAP1206 4.7uf $DIP C42 1 +5V 2 GND $DEF C43 CAP_VSF 330uf $DIP C43 1 PW1_VOUT 2 GND $DEF C44 TNT1206 15uf $DIP C44 1 PW1_VOUT 2 GND $DEF SJ1 JUMPAD_080 $DIP SJ1 1 +3.3V 2 PW1_VOUT ; ------------------------------ ; 1.5V Series Regulator (PW2) ; $DEF VR2 LP3966ES ADJ $DIP VR2 1 +3.3V 2 +3.3V ; Shutdown, Vin 3 GND 6 GND ; Grounds 4 PW2_VOUT 5 PW2_VADJ ; Vout, Sense $DEF C45 TNT1206 15uf $DIP C45 1 +3.3V 2 GND $DEF C46 CAP_VSF 330uf $DIP C46 1 PW2_VOUT 2 GND $DEF C47 TNT1206 15uf $DIP C47 1 PW2_VOUT 2 GND $DEF C48 CAP0805 270pf $DIP C48 1 PW2_VOUT 2 PW2_VADJ $DEF R33 RES1206 1.2K $DIP R33 1 PW2_VOUT 2 PW2_VADJ $DEF R34 RES1206 5.1K $DIP R34 1 GND 2 PW2_VADJ $DEF SJ2 JUMPAD_080 $DIP SJ2 1 +1.5V 2 PW2_VOUT ; -------------------- Test Points/Pads -------------------- ; $DEF TP1 TPOINT $DIP TP1 1 GND $DEF TP2 TPOINT $DIP TP2 1 GND $DEF TP3 TPOINT $DIP TP3 1 GND $DEF TP4 TPOINT $DIP TP4 1 GND $DEF TP5 TPOINT $DIP TP5 1 GND $DEF TP6 TPOINT $DIP TP6 1 GND $DEF TP7 TPOINT $DIP TP7 1 GND ; Scope test point pins ; $DEF TPA TPOINT $DIP TPA 1 _TPOINTA $DEF TPB TPOINT $DIP TPB 1 _TPOINTB ; Additional touch pads on the FPGA ; $DEF SPA TPAD_040 $DIP SPA 1 _IOT001 $DEF SPB TPAD_040 $DIP SPB 1 _IOT002 $DEF SPC TPAD_040 $DIP SPC 1 _IOT003 $DEF SPD TPAD_040 $DIP SPD 1 _IOT004 ; Voltage touch pads ; $DEF T+5V TPAD_040 $DIP T+5V 1 +5V $DEF T+3_3V TPAD_040 $DIP T+3_3V 1 +3.3V $DEF T+1_5V TPAD_040 $DIP T+1_5V 1 +1.5V $DEF T+12V TPAD_040 $DIP T+12V 1 +12V $DEF T-12V TPAD_040 $DIP T-12V 1 -12V ; -------------------- 3.3V Bypassing -------------------- ; $DEF BY100 CAP0805 0.1uf $DIP BY100 1 +3.3V 2 GND $DEF BY101 CAP0805 0.1uf $DIP BY101 1 +3.3V 2 GND $DEF BY102 CAP0805 0.1uf $DIP BY102 1 +3.3V 2 GND $DEF BY103 CAP0805 0.1uf $DIP BY103 1 +3.3V 2 GND $DEF BY104 CAP0805 0.1uf $DIP BY104 1 +3.3V 2 GND $DEF BY105 CAP0805 0.1uf $DIP BY105 1 +3.3V 2 GND $DEF BY106 CAP0805 0.1uf $DIP BY106 1 +3.3V 2 GND $DEF BY107 CAP0805 0.1uf $DIP BY107 1 +3.3V 2 GND $DEF BY110 CAP0805 0.1uf $DIP BY110 1 +3.3V 2 GND $DEF BY111 CAP0805 0.1uf $DIP BY111 1 +3.3V 2 GND $DEF BY112 CAP0805 0.1uf $DIP BY112 1 +3.3V 2 GND $DEF BY113 CAP0805 0.1uf $DIP BY113 1 +3.3V 2 GND $DEF BY114 CAP0805 0.1uf $DIP BY114 1 +3.3V 2 GND $DEF BY115 CAP0805 0.1uf $DIP BY115 1 +3.3V 2 GND $DEF BY116 CAP0805 0.1uf $DIP BY116 1 +3.3V 2 GND $DEF BY117 CAP0805 0.1uf $DIP BY117 1 +3.3V 2 GND $DEF BY118 CAP0805 0.1uf $DIP BY118 1 +3.3V 2 GND $DEF BY119 CAP0805 0.1uf $DIP BY119 1 +3.3V 2 GND $DEF BY120 CAP0805 0.01uf $DIP BY120 1 +3.3V 2 GND $DEF BY121 CAP0805 0.01uf $DIP BY121 1 +3.3V 2 GND $DEF BY122 CAP0805 0.01uf $DIP BY122 1 +3.3V 2 GND $DEF BY123 CAP0805 0.01uf $DIP BY123 1 +3.3V 2 GND $DEF BY124 CAP0805 0.01uf $DIP BY124 1 +3.3V 2 GND $DEF BY125 CAP0805 0.01uf $DIP BY125 1 +3.3V 2 GND $DEF BY126 CAP0805 0.01uf $DIP BY126 1 +3.3V 2 GND $DEF BY127 CAP0805 0.01uf $DIP BY127 1 +3.3V 2 GND $DEF BY128 CAP0805 0.01uf $DIP BY128 1 +3.3V 2 GND $DEF BY129 CAP0805 0.01uf $DIP BY129 1 +3.3V 2 GND $DEF BY130 CAP0805 0.01uf $DIP BY130 1 +3.3V 2 GND $DEF BY190 TNT1206 15uf $DIP BY190 1 +3.3V 2 GND $DEF BY191 TNT1206 15uf $DIP BY191 1 +3.3V 2 GND $DEF BY192 TNT1206 15uf $DIP BY192 1 +3.3V 2 GND $DEF BY193 TNT1206 15uf $DIP BY193 1 +3.3V 2 GND $DEF BY194 TNT1206 15uf $DIP BY194 1 +3.3V 2 GND $DEF BY195 TNT1206 15uf $DIP BY195 1 +3.3V 2 GND $DEF BY196 TNT1206 15uf $DIP BY196 1 +3.3V 2 GND ; -------------------- 1.5V Bypassing -------------------- ; $DEF BY200 CAP0805 0.1uf $DIP BY200 1 +1.5V 2 GND $DEF BY201 CAP0805 0.1uf $DIP BY201 1 +1.5V 2 GND $DEF BY202 CAP0805 0.1uf $DIP BY202 1 +1.5V 2 GND $DEF BY203 CAP0805 0.1uf $DIP BY203 1 +1.5V 2 GND $DEF BY204 CAP0805 0.1uf $DIP BY204 1 +1.5V 2 GND $DEF BY205 CAP0805 0.1uf $DIP BY205 1 +1.5V 2 GND $DEF BY206 CAP0805 0.1uf $DIP BY206 1 +1.5V 2 GND $DEF BY207 CAP0805 0.1uf $DIP BY207 1 +1.5V 2 GND $DEF BY220 CAP0805 0.01uf $DIP BY220 1 +1.5V 2 GND $DEF BY221 CAP0805 0.01uf $DIP BY221 1 +1.5V 2 GND $DEF BY222 CAP0805 0.01uf $DIP BY222 1 +1.5V 2 GND $DEF BY223 CAP0805 0.01uf $DIP BY223 1 +1.5V 2 GND $DEF BY224 CAP0805 0.01uf $DIP BY224 1 +1.5V 2 GND $DEF BY225 CAP0805 0.01uf $DIP BY225 1 +1.5V 2 GND $DEF BY226 CAP0805 0.01uf $DIP BY226 1 +1.5V 2 GND $DEF BY227 CAP0805 0.01uf $DIP BY227 1 +1.5V 2 GND $DEF BY230 TNT1206 15uf $DIP BY230 1 +1.5V 2 GND $DEF BY231 TNT1206 15uf $DIP BY231 1 +1.5V 2 GND $DEF BY232 TNT1206 15uf $DIP BY232 1 +1.5V 2 GND $DEF BY233 TNT1206 15uf $DIP BY233 1 +1.5V 2 GND ; -------------------- +5V Bypassing -------------------- ; $DEF BY300 CAP0805 0.1uf $DIP BY300 1 +5V 2 GND $DEF BY301 CAP0805 0.1uf $DIP BY301 1 +5V 2 GND $DEF BY302 CAP0805 0.1uf $DIP BY302 1 +5V 2 GND $DEF BY310 CAP0805 0.01uf $DIP BY310 1 +5V 2 GND $DEF BY311 CAP0805 0.01uf $DIP BY311 1 +5V 2 GND $DEF BY312 CAP0805 0.01uf $DIP BY312 1 +5V 2 GND $DEF BY313 CAP0805 0.01uf $DIP BY313 1 +5V 2 GND $DEF BY314 CAP0805 0.01uf $DIP BY314 1 +5V 2 GND $DEF BY315 CAP0805 0.01uf $DIP BY315 1 +5V 2 GND $DEF BY316 CAP0805 0.01uf $DIP BY316 1 +5V 2 GND $DEF BY317 CAP0805 0.01uf $DIP BY317 1 +5V 2 GND $DEF BY318 CAP0805 0.01uf $DIP BY318 1 +5V 2 GND $DEF BY325 TNT1206 15uf $DIP BY325 1 +5V 2 GND $DEF BY326 TNT1206 15uf $DIP BY326 1 +5V 2 GND $DEF BY327 TNT1206 15uf $DIP BY327 1 +5V 2 GND $DEF BY328 TNT1206 15uf $DIP BY328 1 +5V 2 GND $DEF BY329 TNT1206 15uf $DIP BY329 1 +5V 2 GND $DEF BY330 TNT1206 15uf $DIP BY330 1 +5V 2 GND $DEF BY331 TNT1206 15uf $DIP BY331 1 +5V 2 GND $DEF BY332 TNT1206 15uf $DIP BY332 1 +5V 2 GND $DEF BY333 TNT1206 15uf $DIP BY333 1 +5V 2 GND ; -------------------- +12V Bypassing -------------------- ; $DEF BY340 CAP0805 0.1uf $DIP BY340 1 +12V 2 GND $DEF BY341 CAP0805 0.1uf $DIP BY341 1 +12V 2 GND $DEF BY345 CAP1206 4.7uf $DIP BY345 1 +12V 2 GND $DEF BY346 CAP1206 4.7uf $DIP BY346 1 +12V 2 GND ; -------------------- -12V Bypassing -------------------- ; $DEF BY350 CAP0805 0.1uf $DIP BY350 1 GND 2 -12V $DEF BY351 CAP0805 0.1uf $DIP BY351 1 GND 2 -12V $DEF BY355 CAP1206 4.7uf $DIP BY355 1 GND 2 -12V ; ------------------------------ ; Mounting holes around the perimeter of the board ; $DEF MH01 250PAD_125 $DIP MH01 1 GND $DEF MH02 250PAD_125 $DIP MH02 1 GND $DEF MH03 250PAD_125 $DIP MH03 1 GND $DEF MH04 250PAD_125 $DIP MH04 1 GND $DEF MH05 250PAD_125 $DIP MH05 1 GND $DEF MH06 250PAD_125 $DIP MH06 1 GND $DEF MH07 250PAD_125 $DIP MH07 1 GND $DEF MH08 250PAD_125 $DIP MH08 1 GND $DEF MH09 250PAD_125 $DIP MH09 1 GND $DEF MH10 250PAD_125 $DIP MH10 1 GND $DEF MH11 250PAD_125 $DIP MH11 1 GND $DEF MH12 250PAD_125 $DIP MH12 1 GND $DEF MH13 250PAD_125 $DIP MH13 1 GND $DEF MH14 250PAD_125 $DIP MH14 1 GND $DEF MH15 250PAD_125 $DIP MH15 1 GND $DEF MH16 250PAD_125 $DIP MH16 1 GND