/* **********************************************************************
 * *                                                                    *
 * *             RVP8/Rx PCI Card Private Driver Definitions            *
 * *                                                                    *
 * **********************************************************************
 * File: rda/pcicards/rvp8rx_def.h
 *
 *                        COPYRIGHT (c) 2002  BY
 *          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
 * 
 * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
 * ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
 * INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
 * COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
 * OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
 * TRANSFERED.
 */
#ifndef SIGMET_RVP8RX_DEF_H
#define SIGMET_RVP8RX_DEF_H 1

/* ------------------------------
 * Opaque driver information structure
 */
struct tgBankHeap {	  /* Lookup info for one bank of pulses */
  SINT4 iBankStart ;	  /*   This bank starts here in heap */
  SINT4 nPulses ;	  /*   Number of pulses in this bank */
  SINT4 iLoopback ;	  /*   Last pulse loops back to this one */
} ;

struct rvp8rx_info {		
  /* Card file descriptors and memory pointers
   */
  SINT4 sizes[4] ;		/* Sizes and channels for each mapped */
  SINT4 chans[4] ;		/*   PCI or kernel memory segment. */
  volatile struct rvp8rx_csr    *csr ;	/* ==> Control/Status area */
  volatile struct rvp8rx_master *mas ;	/* ==> Master FPGA memory */
  volatile struct rvp8rx_filter *flt ;	/* ==> Filter FPGA memory */
  volatile UINT4 *dma ;		        /* ==> Kernel DMA area */

  char sDevName[40] ;		/* Device name */

  UINT4 iL1CacheBytes ;		/* PCI/DMA/CPU L1 cacheline size in bytes */
  UINT4 iDwordCacheMask ;	/*   and mask for DWord transfers. */

  UINT4 lOpened ;		/* Device is opened */
  UINT4 lSecUnit ;		/* Secondary unit (of possible two) */
  struct rda_boardinfo openInfo ;

  /* Diagnostic test results, and related information.
   */
  UINT4 dgBits ;		/* Summary error bits */
#define RX8DG_MIRROR     0x00000001 /* PCI mirror register */
#define RX8DG_MEM0       0x00000002 /* Memory 0 (U10/U11) failure */
#define RX8DG_MEM1       0x00000004 /* Memory 1 (U12/U13) failure */
#define RX8DG_DMA        0x00000008 /* DMA transfer data check */
#define RX8DG_DNLOCNT_A  0x00000010 /* Downlink local counter test */
#define RX8DG_DNLOCNT_B  0x00000020
#define RX8DG_DNLOCNT_C  0x00000040
#define RX8DG_DNLOCNT_D  0x00000080
#define RX8DG_SIGDET     0x00000100 /* No fiber signal detected */
#define RX8DG_MONOCLOCK  0x00000200 /* Clock monotonicity */
#define RX8DG_RCVSTS_A   0x00000400 /* Receiver status bits & switches */
#define RX8DG_RCVSTS_B   0x00000800
#define RX8DG_RCVWORDS_A 0x00001000 /* Test word pattern from receiver */
#define RX8DG_RCVWORDS_B 0x00002000
#define RX8DG_RCVBYTES   0x00004000 /* Test byte pattern from receiver */
#define RX8DG_RTRIPJIT_A 0x00008000 /* Round trip delay and jitter */
#define RX8DG_RTRIPJIT_B 0x00010000
#define RX8DG_IQLOGGER_A 0x00020000 /* (I,Q) data logger */
#define RX8DG_IQLOGGER_B 0x00040000
#define RX8DG_IQLOGGER_C 0x00080000

#define RX8DG_FIRXBANK   0x00100000 /* FIR X-Bank short filter      \ */
#define RX8DG_FIRYBANK   0x00200000 /* FIR Y-Bank short filter       \ Rev.A/B */
#define RX8DG_FIRCASCADE 0x00400000 /* FIR X&Y banks 12-bit cascade  / Boards  */
#define RX8DG_FIRGANGED  0x00800000 /* FIR X&Y banks 16-bit ganged  / */

#define RX8DG_FIRLONG    0x00100000 /* Commputation of long FIR     \ Rev.C & Up */
#define RX8DG_UPLINKBER  0x00400000 /* UpLink Bit Error Rate check   >  Boards   */
#define RX8DG_DNLINKBER  0x00800000 /* DnLink Bit Error Rate check  / */

#define RX8DG_IQNORM     0x01000000 /* (I,Q) Normalize/Pack */

  UINT4 dgMirrorBits[2] ;	/* PCI mirror errors (0-->1 and 1-->0 errors) */
  UINT4 dgMemBits[2] ;		/* Memory error bits (two SRAMS) */

  /* Configuration information about the board itself, which can not
   * be deduced from the board alone, i.e., must be supplied to the
   * driver externally.
   */
  FLT4  fAqClk ;		/* Data acquisition clock, MHz */
  FLT4  fTgClk ;		/* Trigger generation clock, MHz */
  UINT4 lifsign ; 		/* IF increases for an approaching target */

  FLT4    fifreqs[MAXFREQSPERRX] ;    /* Radar intermediate frequency(ies) (MHz) */
  SINT4 iModsAQIF[MAXFREQSPERRX][2] ; /* Integer ratio of AQ and each IF */

  /* All PCI access to the board's CSR registers are locked by this
   * one mutex.  Although this may sometimes lockout two unrelated
   * processes that would not actually interfere with each other, it
   * removes any worry about deadly embraces caused by order of locks
   * and order of subroutine calls.
   */
  pthread_mutex_t CSRMutex ;	/* For indivisible CSR access */

  /* Likewise, the following mutex should bracket all indivisible
   * sequences of driver activity that can not be handled by the CSR
   * lock alone.
   */
  pthread_mutex_t SeqMutex ;	/* For indivisible sequential access */

  /* Access to DIF hardware and DMA transfers are each locked by a
   * dedicated mutex.
   */
  pthread_mutex_t DIFMutex ;	/* Only one Direct IF user at a time */
  pthread_mutex_t DMAMutex ;	/* Only one DMA channel onboard */

  /* Association between BTime and SysTime.  Two copies and valid flag
   * make it possible to read safely without a mutex.
   */
  struct rvp8AssocBtime assocBtimes[2] ;
  SINT4 iValidAssocBtime ;

  /* Information about the onboard general purpose timer(s) and the
   * front panel display.
   */
  struct gpTimerInfo gpTimerInfo ;
  struct  matorbInfo  matorbInfo ;

  /* IFD downlink and status
   */
  struct ifd_status IFDSts ;	/* Status bits from the IFD */

  UINT4 lIFDTempOnChip ;	/* Temperature measurement, MAX vs FPGA */

  /* Uplink Transmitter State
   */
  UINT4 lUsePinMap ;		/* Optional 3-word pinmap format */
  UINT4 iPinMap ;
  UINT4 iPinErr ;
  UINT4 lUseOld16 ;		/* Optional old 16-bit format */
  UINT4 iOld16 ;
  UINT4 lUseNoise ;		/* Optional noise generator code */
  UINT4 iNoise ;
  UINT4 lUseSwaps ;		/* Optional input swapping */
  UINT4 iSwaps ;

  /* Trigger Generator state
   */
  struct rvp8TgInfo tgInfo ;	/* Setup information for triggers */

  SINT4 iTgBankReq ;	        /* Requested trigger bank */
  SINT4 iTgBank ;		/* Committed trigger bank */

  UINT4 lTgBlanked ;		/* Trigger is (should be) blanked now */
  UINT4 iTgBlankBtime ;		/* Time that blanking was last changed */

  UINT4 lTgHiHeap ;		/* TRUE if high heap is being written */
  volatile UINT4 *pTgHeapMem ;	/* ==> Base of heap implied by lTgHiHeap */
  SINT4 iTgHeap ;		/* ==> Next word to write in RAM heap */
  SINT4 iTgOpAddr ;		/* ==> Data opcode for back patching */
  SINT4 iTgOpNum ;		/* Number of data words in last opcode */

  UINT4 iPulseCountLast ;	/* Last hardware counter value */
  UINT4 iTrigCountAccum ;	/* Accumulating trigger count */

  pthread_mutex_t BankMutex ;	/* Special lock on the following BANK elements */
  struct rvp8TgPulse *pBanks ;  /*   ==> Bank/Wave heap of defined pulses */
  SINT4 nBankItems ;		/*   Number of defined items in the heap */
  SINT4 iFirstBank ;		/*   First bank number defined in the heap */
  struct tgBankHeap bankInfo    /*   Array of lookup table info for each */
    [ BIT(RX8BANKBITS) ] ;	/*     trigger bank in the above heap. */

  /* Range mask, (I,Q) filter, and data logger
   */
  void *pRngMaskGen ;		/* ==> range mask generation memory */
} ;

/* ------------------------------
 * Macros and function prototypes that are used only within the
 * RVP8/Rx driver
 */
SINT4 iRvp8RxTrigRunbankPreLocked_
( Rvp8Rx *pDev_a, SINT4 iBank_a, UINT4 iFlags_a ) ;

#define LRVP8RXTRIGBANKPENDING( CSR )					\
  ( ( (CSR) & (BIT(RX8TGCSR_RUNNING) | BIT(RX8TGCSR_PENDING)) ) ==	\
    (         (BIT(RX8TGCSR_RUNNING) | BIT(RX8TGCSR_PENDING)) ) )

#endif /* #ifndef SIGMET_RVP8RX_DEF_H */
