-- **********************************************************************
-- *                                                                    *
-- *     Hardware Register Mappings for the RVP8/Rx Receiver Board      *
-- *                                                                    *
-- **********************************************************************
-- File: rda/pcicards/rvp8rx.inc
--
--                        COPYRIGHT (c) 2004  BY
--          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
-- 
-- THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
-- ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
-- INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
-- COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
-- OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
-- TRANSFERED.
--

-- = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-- This file must be manually maintained in parallel with its C
--   companion file: rvp8rx.h.  The syntax between C and AHDL
--        is too different to try to patch automatically.
-- = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

-- **************************************
-- *                                    *
-- * RVP8/Rx Control/Status Definitions *
-- *                                    *
-- **************************************

CONSTANT RX8CSRSZ             = 64 ;	-- CSR decoded address space (DWORDs)
CONSTANT RX8CSRHIB = LOG2(RX8CSRSZ) - 1 ;

-- ------------------------------
-- CAUTION: Address 0x00 is RESETADDR
-- CAUTION: Address 0x01 is ISR_ADDR

-- ------------------------------
-- Board Edge LEDs.  Note that the "Always ON" code is assigned the
-- value zero so that all of the LEDs light up upon reset.
--
CONSTANT RX8REDLED       = H"03" ;	-- Red LED options
  CONSTANT RX8REDLED_ON      = 0 ; 	--   On always
  CONSTANT RX8REDLED_OFF     = 1 ;	--   Off always
  CONSTANT RX8REDLED_PCIACT  = 2 ;	--   Shows PCI access

CONSTANT RX8GRNLED       = H"04" ;	-- Green LED options
  CONSTANT RX8GRNLED_ON      = 0 ; 	--   On always
  CONSTANT RX8GRNLED_OFF     = 1 ;	--   Off always

CONSTANT RX8SIGLED       = H"05" ;	-- Green "signal detect" LED options
  CONSTANT RX8SIGLED_ON      = 0 ; 	--   On always
  CONSTANT RX8SIGLED_OFF     = 1 ;	--   Off always
  CONSTANT RX8SIGLED_DNLNK   = 2 ;	--   Shows downlink present

-- ------------------------------
-- Control/Status from the remote IFD.
--
CONSTANT RX8RCVR         = H"06" ;	-- Status of the receiver box
  -- The low 16-bits are the low bits of the IFD status word.  Higher
  -- bits are read from RX8IFDSTS0/1.
  --
  CONSTANT RX8RCVR_SIGDET    = 16 ;	--   Downlink signal detected
  CONSTANT RX8RCVR_DIRECTIF  = 17 ;	--   Output 12-bit samples directly
  CONSTANT RX8RCVR_DIAGCNT   = 18 ;	--   Diagnostic counter output
  CONSTANT RX8RCVR_NOSYNC    = 19 ;	--   Ignore RXSYNC input
--CONSTANT RX8RCVR_REQRXCLK  = 20 ;	--   Request to lock AQCLK2X to downlink
--CONSTANT RX8RCVR_REQXTAL   = 21 ;	--     clock or internal crystal.
--CONSTANT RX8RCVR_STSRXCLK  = 22 ;	--   Actual selection
  CONSTANT RX8RCVR_UPLINKOK  = 23 ;	--   Uplink being received okay

-- ------------------------------
-- Manchester encoded uplink bit definitions.  The payload bits are
-- carried on top of a synchronous self-framing protocol, and consist of
-- 8-bits of data and a single Command-vs-Data flag.  Writing to the CSR
-- queues a word for delivery to the IFD; reading from the CSR returns
-- the number of used slots in the FIFO.
--
CONSTANT UPFIFO              = H"07" ;	-- Uplink command stream and status

CONSTANT UPFIFO_DATAWIDTH    =    9 ;	-- Total number of payload bits
CONSTANT UPFIFO_ADDRWIDTH    =    0 ;	-- Number of address bits
CONSTANT UPFIFO_ADDRESS      =    0 ;	--   and the value therein.
CONSTANT UPFIFO_DEPTH        =  512 ;	-- Depth of PCI-->SyncTx FIFO

CONSTANT UPFIFO_CMDBIT       =    8 ;	-- Command (versus data) bit
CONSTANT UPFIFO_KEEPALIVE    = H"00" ;	-- Inserted periodically on healthy link
CONSTANT UPFIFO_RESET        = H"01" ;	-- Reset the entire IFD
CONSTANT UPFIFO_BOOTCHIP     = H"02" ;	-- Command to 7064 boot chip (data follows)
CONSTANT UPFIFO_TEMPCHIP     = H"04" ;	-- Sample temperature, low bits = <RSV,ONCHIP>
CONSTANT UPFIFO_PLLCLK       = H"08" ;	-- LMX2306 , low bits = <CLK,DATA,LE>
CONSTANT UPFIFO_JTAG         = H"F0" ;	-- JTAG cmd, low bits = <ENAB,TMS,TDI,TCK>

-- ------------------------------
-- System time register, counts in units of the acquisition clock.  The
-- low four bits are zeroed, thereby giving a PCI resolution of approx
-- one half microsecond.
--
CONSTANT RX8SYSTIME      = H"08" ;	-- Read-only time

-- ------------------------------
-- (I,Q) Data Logger Registers
--
CONSTANT RX8IQLCSR       = H"09" ;	-- Control/Status
  CONSTANT RX8IQLCSR_RUNREQ  = 0 ;	--   Request to run (I,Q) logger
  CONSTANT RX8IQLCSR_RUNNING = 1 ;	--   Logger is running now
  CONSTANT RX8IQLCSR_IQHCLR  = 2 ;	--   Clear IQHEAD register
  CONSTANT RX8IQLCSR_PULCLR  = 3 ;	--   Clear PULSES register
  CONSTANT RX8IQLCSR_NOWRAP  = 4 ;	--   Kill RUNREQ on Data/Hdr wrap

CONSTANT RX8IQHEAD       = H"0A" ;	-- (I,Q) write ptr (read-only)

CONSTANT RX8PULCNT       = H"0B" ;	-- Pulse counter (read-only)
  CONSTANT RX8PULCNTHIB      = 15 ;	--   High bit of counter

-- ------------------------------
-- Local side configuration of DMA transfers.
--
CONSTANT RX8DMACSR       = H"0C" ;	-- Control/Status
  CONSTANT RX8DMACSR_RUNREQ  = 0 ;	--   Fill FIFO from MPM reads

CONSTANT RX8DMADDR       = H"0D" ;	-- DMA read address from MPM

-- ------------------------------
-- Front panel connector I/O and signal assignments
--
CONSTANT RX8PANEL        = H"0E" ;	-- Control/Status
  CONSTANT RX8PANEL_TG0SEL   = 0 ;	--   Trigger 0, or Polar 0
  CONSTANT RX8PANEL_TG1SEL   = 1 ;	--   Trigger 1, or Polar 1

-- ------------------------------
-- Extended IFD status.  These additional status bits are sent down from
-- the IFD on each K28.5 framing cycle.
--
CONSTANT RX8IFDSTS0      = H"10" ;	-- IFD status bits [ 47..16 ]
CONSTANT RX8IFDSTS1      = H"11" ;	-- IFD status bits [ 79..48 ]

-- ------------------------------
-- Bit-Error-Rate monitors for three downlink channels and one uplink
-- channel.  These four 8-bit counters will max out at 0xFF, and are
-- cleared every time they are read.
--
CONSTANT RX8BERR         = H"14" ;	-- <UpLink , Rx-C , Rx-B , Rx-A>

-- ------------------------------
-- DSP/FIR Filter Control (Rev.C and higher boards)
--
CONSTANT RX8DSPCSR       = H"15" ;	-- Control/Status
  CONSTANT RX8DSPCSR_RUNREQ  =  0 ;	--   Request to run FIR filters
  CONSTANT RX8DSPCSR_DIAGCNT =  1 ;	--   Apply diagnostic counter input
  CONSTANT RX8DSPCSR_LOWSUM  =  2 ;	--   Shift output to get LSBs exactly

  CONSTANT RX8DSPCSR_NVECS0  =  4 ;	--   Number of (I,Q) vecs (minus 1)
  CONSTANT RX8DSPCSR_NVECS1  =  5 ;	--     generated per range bin.

  CONSTANT RX8DSPCSR_DCMATE0 =  8 ;	--   Decimation factor (minus 2)
  CONSTANT RX8DSPCSR_DCMATE1 =  9 ;
  CONSTANT RX8DSPCSR_DCMATE2 = 10 ;
  CONSTANT RX8DSPCSR_DCMATE3 = 11 ;
  CONSTANT RX8DSPCSR_DCMATE4 = 12 ;
  CONSTANT RX8DSPCSR_DCMATE5 = 13 ;

  CONSTANT RX8DSPCSR_NDSPS0  = 16 ;	-- Number of DSPs for which this
  CONSTANT RX8DSPCSR_NDSPS1  = 17 ;	--   FPGA has been compiled.
  CONSTANT RX8DSPCSR_NDSPS2  = 18 ;
  CONSTANT RX8DSPCSR_NDSPS3  = 19 ;

-- The coefficient lookup tables are write-only from the PCI side.  They
-- are written one word at a time from this address:
--
--    [ 31..24 ] : Which RAM bank to write (for multiplier 0, 1, 2, etc)
--    [ 23..16 ] : 8-bit address within the selected coefficient RAM
--    [ 15.. 0 ] : 16-bit signed coefficient value
--
-- The 8-bit coefficient addresses are organized as follows:
--
--    [    7 ] : Selects First/Second set of 4x clocked decimation registers
--    [ 6..0 ] :          0 -->   DECIMATE-1  Coefficients for I of first vector
--                 DECIMATE --> 2*DECIMATE-1  Coefficients for Q of first vector
--               2*DECIMATE --> 3*DECIMATE-1  Coefficients for I of second vector
--               3*DECIMATE --> 4*DECIMATE-1  Coefficients for Q of secton vector
--                                            etc, according to number of vectors
--
CONSTANT RX8DSPCOEF      = H"16" ;	-- Coefficient registers (write only)
  CONSTANT RX8DSPCOEF_WILDB  = H"FF" ;	--   Wild card bank (all banks written)

-- ------------------------------
-- Front Panel Display Control
--
CONSTANT RX8FPDCSR       = H"20" ;	-- Control/Status
CONSTANT RX8FPDATA       = H"21" ;	-- Character read/write

-- ------------------------------
-- Trigger Generator
--
CONSTANT RX8TGCSR        = H"22" ;	-- Control/Status
  CONSTANT RX8TGCSR_RUNREQ   =  0 ;	--   Request to begin running
  CONSTANT RX8TGCSR_RUNNING  =  1 ;	--   Real time mode is running (RD-Only)
  CONSTANT RX8TGCSR_HEAPREQ  =  2 ;	--   Requested Hi/Lo memory heap
  CONSTANT RX8TGCSR_CURHEAP  =  3 ;	--   Memory heap currently in use (RD-Only)
  CONSTANT RX8TGCSR_DFBANK0  =  4 ;	--   Requested bank of waveforms
  CONSTANT RX8TGCSR_DFBANK1  =  5 ;
  CONSTANT RX8TGCSR_DFBANK2  =  6 ;
  CONSTANT RX8TGCSR_DFBANK3  =  7 ;
  CONSTANT RX8TGCSR_DFBANK4  =  8 ;
  CONSTANT RX8TGCSR_DFBANK5  =  9 ;
  CONSTANT RX8TGCSR_EXTERN   = 12 ;	--   Use external trigger source
  CONSTANT RX8TGCSR_XSYNCH   = 13 ;	--   Allow synchronous trig lineup
  CONSTANT RX8TGCSR_RISING   = 14 ;	--   Use rising edge of trigger
  CONSTANT RX8TGCSR_TIMEOUT  = 15 ;	--   Missing external trigger (RD-Only)
  CONSTANT RX8TGCSR_TOBANK   = 16 ;	--   Running with timeout bank (RD-Only)
  CONSTANT RX8TGCSR_RESETREQ = 17 ;	--   Reset the trig generator (WR-Only)
  CONSTANT RX8TGCSR_PENDING  = 18 ;	--   Pending/Busy with TGNEW... (RD-Only)
  CONSTANT RX8TGCSR_SNAPPED  = 19 ;	--   Wr1->Set, Rd: TGNEW... bits accepted
  CONSTANT RX8TGCSR_TGNEW    = 20 ;	--   Request to begin new Bank/Heap
  CONSTANT RX8TGCSR_TGNEWGP0 = 21 ;	--   Requests to begin new Bank/Heap
  CONSTANT RX8TGCSR_TGNEWGP1 = 22 ;	--     when the corresponding GPTimer
  CONSTANT RX8TGCSR_TGNEWGP2 = 23 ;	--     fires an interrupt.
  CONSTANT RX8TGCSR_PHASELO  = 24 ;	--   Bits of Tx phase for the first
  CONSTANT RX8TGCSR_PHASEHI  = 31 ;	--     pulse of newly starting bank.

-- ------------------------------
-- Legacy serial uplink to the IFD.  This is the same data stream that
-- runs on the coax cable to RVP7 vintage IFDs.
--
CONSTANT RX8UPCSR        = H"23" ;	-- Control/Status
  CONSTANT RX8UPCSR_RUNREQ   =  0 ;	--   Run from burst triggers
  CONSTANT RX8UPCSR_SENDING  =  1 ;	--   Transmitter is running now
  CONSTANT RX8UPCSR_HEAPREQ  =  2 ;	--   Request and Current Selection
  CONSTANT RX8UPCSR_HEAPSEL  =  3 ;	--     of Hi/Lo memory heap.
  CONSTANT RX8UPCSR_DIAGX    =  4 ;	--   IFD diagnostic bits
  CONSTANT RX8UPCSR_DIAGY    =  5 ;
  CONSTANT RX8UPCSR_LEDON    =  6 ;	--   IFD Green LED On, or Off, or
  CONSTANT RX8UPCSR_LEDOFF   =  7 ;	--     follow downlink signal detect.
  CONSTANT RX8UPCSR_SINGLE   =  8 ;	--   Generate a single transmission
  CONSTANT RX8UPCSR_IFDRESET =  9 ;	--   Reset the remote IFD

-- ------------------------------
-- Direct IF data sample storage.
--
CONSTANT RX8DIFCSR       = H"24" ;	-- Control/Status
  CONSTANT RX8DIFCSR_WRCONT  =  0 ;	--   Continuous IF recording
  CONSTANT RX8DIFCSR_NOWAIT  =  1 ;	--   Don't wait for start of pulse
  CONSTANT RX8DIFCSR_WTBANK  =  2 ;	--   If waiting, then also wait for BANK
  CONSTANT RX8DIFCSR_BANK0   =  4 ;	--   Trigger bank to wait for
  CONSTANT RX8DIFCSR_BANK1   =  5 ;
  CONSTANT RX8DIFCSR_BANK2   =  6 ;
  CONSTANT RX8DIFCSR_BANK3   =  7 ;
  CONSTANT RX8DIFCSR_BANK4   =  8 ;
  CONSTANT RX8DIFCSR_BANK5   =  9 ;

CONSTANT RX8DIFPCNT      = H"25" ;	-- Desired pulse count
CONSTANT RX8DIFADDR      = H"26" ;	-- IF data write address
  CONSTANT RX8DIFMAXP = 255 ;		-- Maximum pulse count

-- ------------------------------
-- Range mask generation
--
CONSTANT RX8RNGCSR       = H"28" ;	-- Control/Status
  CONSTANT RX8RNGCSR_RUNREQ  =  0 ;	--   Request to begin running
  CONSTANT RX8RNGCSR_RUNNING =  1 ;	--   Real time mode is running

-- ------------------------------
-- FIR Filter Control (Rev.A and Rev.B boards)
--
CONSTANT RX8FIRCSR       = H"29" ;	-- Control/Status
  CONSTANT RX8FIRCSR_RUNREQ  =  0 ;	--   Request to run FIR filters
  CONSTANT RX8FIRCSR_YDIV16  =  1 ;	--   Divide Y output data by 16
  CONSTANT RX8FIRCSR_XOUTZER =  2 ;	--   Zero the X filter outputs
  CONSTANT RX8FIRCSR_YOUTZER =  3 ;	--   Zero the Y filter outputs

  CONSTANT RX8FIRCSR_XIDAT16 =  4 ;	--   X:DAT<15..4> (IF data hi bits)
  CONSTANT RX8FIRCSR_XICNT16 =  5 ;	--   X:CNT<15..4> (Counter hi bits)
  CONSTANT RX8FIRCSR_XICNT12 =  6 ;	--   X:CNT<11..0> (Counter lo bits)

  CONSTANT RX8FIRCSR_YIDAT04 =  8 ;	--   Y:(0,0,0,0,0,0,0,0, DAT<3..0>)
  CONSTANT RX8FIRCSR_YICNT04 =  9 ;	--   Y:(0,0,0,0,0,0,0,0, CNT<3..0>)
  CONSTANT RX8FIRCSR_YICNT12 = 10 ;	--   Y: CNT<11..0> (Counter lo bits)
  CONSTANT RX8FIRCSR_YICSCAD = 11 ;	--   Y:ROUT<11..0> (Cascade from X)

  CONSTANT RX8FIRCSR_DCMATE0 = 12 ;	--   Decimation factor (minus 2)
  CONSTANT RX8FIRCSR_DCMATE1 = 13 ;
  CONSTANT RX8FIRCSR_DCMATE2 = 14 ;
  CONSTANT RX8FIRCSR_DCMATE3 = 15 ;

  CONSTANT RX8FIRCSR_NCHIPS0 = 16 ;	--   Number of filter chips (exactly)
  CONSTANT RX8FIRCSR_NCHIPS1 = 17 ;	--     contributing to the output sum.

  CONSTANT RX8FIRCSR_NVECS0  = 18 ;	--   Number of (I,Q) vecs (minus 1)
  CONSTANT RX8FIRCSR_NVECS1  = 19 ;	--     generated per range bin.

CONSTANT RX8LFDATA       = H"2A" ;	-- LF3320's "LF" interface, data

CONSTANT RX8LFCTRL       = H"2B" ;	-- LF3320's "LF" interface, control
  CONSTANT RX8LFCTRL_XLDA    = 0 ;	--   X filter, A channel
  CONSTANT RX8LFCTRL_XLDB    = 1 ;	--   X filter, B channel
  CONSTANT RX8LFCTRL_YLDA    = 2 ;	--   Y filter, A channel
  CONSTANT RX8LFCTRL_YLDB    = 3 ;	--   Y filter, B channel
  CONSTANT RX8LFCTRL_CHIP0   = 4 ;	--   Enable writing for the three
  CONSTANT RX8LFCTRL_CHIP1   = 5 ;	--     sets of LF3320 chips.
  CONSTANT RX8LFCTRL_CHIP2   = 6 ;

-- ------------------------------
-- FIR Output Data Word Packer
--
CONSTANT RX8IQPCSR       = H"2C" ;	-- Control/Status
  CONSTANT RX8IQPCSR_RUNREQ  =  0 ;	--   Request to run data packing
  CONSTANT RX8IQPCSR_DIRECT  =  1 ;	--   Direct copy of 32-bit FIR values

-- ------------------------------
-- General purpose Counter/Timers
--
CONSTANT RX8TIMER0       = H"2D" ;	-- Timers 0-2 Control/Status
CONSTANT RX8TIMER1       = H"2E" ;
CONSTANT RX8TIMER2       = H"2F" ;

  CONSTANT RX8TIMER0_NBITS   = 24 ;	-- Number of bits in timers 0-2
  CONSTANT RX8TIMER1_NBITS   = 12 ;
  CONSTANT RX8TIMER2_NBITS   = 12 ;
					-- Timer clock sources
  CONSTANT RX8TIMER_CLK1MHZ  =  0 ;	--   1MHz (Timer #0 only)
  CONSTANT RX8TIMER_CLK1KHZ  =  0 ;	--   1KHz (Timers #1 & #2)
  CONSTANT RX8TIMER_CLKTRIG  =  1 ;	--   Trigger pulses (all timers)
  CONSTANT RX8TIMER_CLKIOSHR =  2 ;	--   I/O-62 shared (Line #N -> Timer #N)

-- ------------------------------
-- PCI Read/Write 32-bit diagnostic mirror
--
CONSTANT RX8MIRROR       = H"3E" ;	-- Reads back what's written

-- ------------------------------
-- Softplane common control/status register.  Bit definitions can be
-- found in rda_modules.inc.
--
CONSTANT RX8SPLCOM       = H"3F" ;

-- ************************************
-- *                                  *
-- * RVP8/Rx Master FPGA Memory Block *
-- *                                  *
-- ************************************

CONSTANT RX8MASTERSZ     = H"100000" ;	-- Memory size (1M DWORDs)
CONSTANT RX8MASTERHIB = LOG2(RX8MASTERSZ) - 1 ;

CONSTANT RX8IQLMEM       = H"000000" ;	-- (I,Q) logger base address
CONSTANT RX8IQLSIZE      = H"070000" ;	--   and size.

CONSTANT RX8PHDRMEM      = H"070000" ;	-- Pulse header table base
CONSTANT RX8PHDRSIZE     = H"004000" ;	--   address and size.


-- ************************************
-- *                                  *
-- * RVP8/Rx Filter FPGA Memory Block *
-- *                                  *
-- ************************************

CONSTANT RX8FILTERSZ     = H"100000" ;	-- Memory size (1M DWORDs)
CONSTANT RX8FILTERHIB = LOG2(RX8FILTERSZ) - 1 ;

CONSTANT RX8LINKMEM      = H"000100" ;	-- IFD uplink transmitter memory
CONSTANT RX8LINKSIZE     = H"000020" ;	--   and size.

CONSTANT RX8RNGMEM       = H"004000" ;	-- Range mask data pattern memory
CONSTANT RX8RNGSIZE      = H"004000" ;	--   and size.

					-- Hole: ( 0x08000 - 0x0FFFF )

CONSTANT RX8DIFMEM       = H"010000" ;	-- Direct IF data sample memory
CONSTANT RX8DIFSIZE      = H"010000" ;	--   and size.
  CONSTANT RX8DIFMAGIC     = H"03BF" ;	-- Magic number at start of each pulse
					--   (upper RX8BANKBITS bits are BANK #)

CONSTANT RX8TGDMEM       = H"040000" ;	-- Trigger generator memory
CONSTANT RX8TGDSIZE      = H"040000" ;	--   and size.

  -- Opcodes in pulse descriptor words.  These are located in low
  -- memory for the start of each sequence, as well as within the
  -- sequences themselves for each new pulse.
  --
  CONSTANT RX8TGADRHIB     = 16 ;	-- High bit of address field
  CONSTANT RX8TGWAVEINC    = 17 ;	-- "Increment waveform" opcode bit
  CONSTANT RX8TGINTABLE    = 18 ;	-- "Interruptible" opcode bit
  CONSTANT RX8TGPHASELO    = 24 ;	-- Low and high bits of Tx phase
  CONSTANT RX8TGPHASEHI    = 31 ;

  -- Opcodes in pattern control words within each pulse
  --
  CONSTANT RX8TGCNTHIB     = 15 ;	-- High bit of iteration count field
  CONSTANT RX8TGDATA       = 16 ;	-- "Data" vs "Hold" opcode bit
  CONSTANT RX8TGCONT       = 17 ;	-- "Continue" opcode bit

  CONSTANT RX8BANKBITS     =  6 ;	-- Number of bits in trigger bank

-- ***************************************
-- *                                     *
-- *  IFD Status and Uplink Definitions  *
-- *                                     *
-- ***************************************

-- The 72-MBaud RVP8 Rx-->IFD uplink protocol transmits the following two
-- types of information continuously:
-- 
--   * The legacy realtime uplink bit stream L[i], delivered with no more
--     than 1/36 microsecond of edge quantization.
-- 
--   * An arbitrary data stream D[j] delivered at 18-MBaud.
-- 
-- The uplink bits are effectively blocked into repeating groups of four,
-- the first and third of which represent legacy bits L[i] and ~L[i+1],
-- and the second and fourth are either 01 or 10 according to D[j].  We
-- encode two legacy bits and one data bit into every group of four line
-- bits.  This simple encoding accomplishes the following:
-- 
-- DC Balance
-- ----------
-- The Manchester coding of the D[j] bits clearly results in DC balance.
-- However, the L[i]/~L[i+1] bit pairs will also be DC balanced on the
-- average because the legacy uplink does not contain high frequencies
-- that could alias back down to DC after this pseudo +1/-1 mixing step.
-- 
-- Run Length
-- ----------
-- The two Manchester bits in every 4-bit group prevent the line from
-- ever remaining in the same state for more than three bauds in a row.
-- 
-- Framing/Acquisition
-- -------------------
-- When the L[i] and D[j] streams are both idle the line state will be a
-- repeating 0-0-1-1 pattern.  This allows the IFD to acquire the edges
-- of the individual bits as well as the groups-of-four bits.  The link
-- will be considered running when the idle pattern is seen for 10usec.
-- 
-- Error Detection
-- ---------------
-- There are three conditions that will result in loss of the link:
-- 
--   * More than one transition in the decoded L[i] bits in less than
--     600ns.  This matches the shortest realtime legacy pulse length
--     that will ever be transmitted.
-- 
--   * More than 100usec of sustained high level in the decoded L[i]
--     bits.  This matches the longest realtime legacy high level.
-- 
--   * An encoded D[j] bit that is not either 10 or 01.

-- ------------------------------
-- Constants defining serial uplink bit times for the legacy uplink
-- format used by the RVP7 IFD.
--
CONSTANT LBIT_START  =  0 ;	-- The "start" bit that ends the burst
CONSTANT LBIT_CHK0HI =  1 ;	-- Noise immunity check bits
CONSTANT LBIT_CHK1HI =  2 ;
CONSTANT LBIT_CHK2LO =  3 ;
CONSTANT LBIT_AFC15  =  4 ;	-- Bits of serial AFC code
CONSTANT LBIT_AFC14  =  5 ;
CONSTANT LBIT_AFC13  =  6 ;
CONSTANT LBIT_AFC12  =  7 ;
CONSTANT LBIT_AFC11  =  8 ;
CONSTANT LBIT_AFC10  =  9 ;
CONSTANT LBIT_AFC9   = 10 ;
CONSTANT LBIT_AFC8   = 11 ;
CONSTANT LBIT_AFC7   = 12 ;
CONSTANT LBIT_AFC6   = 13 ;
CONSTANT LBIT_AFC5   = 14 ;
CONSTANT LBIT_AFC4   = 15 ;
CONSTANT LBIT_AFC3   = 16 ;
CONSTANT LBIT_AFC2   = 17 ;
CONSTANT LBIT_AFC1   = 18 ;
CONSTANT LBIT_AFC0   = 19 ;
CONSTANT LBIT_RESET  = 20 ;	-- Full reset request
CONSTANT LBIT_CMDATA = 21 ;	-- Command/Data
CONSTANT LBIT_DIAGX  = 22 ;	-- Diagnostic bits
CONSTANT LBIT_DIAGY  = 23 ;
CONSTANT LBIT_LED    = 24 ;
CONSTANT LBIT_DONE   = 25 ;	-- All done

-- The 16-bit words can optionally be interpreted as a 4-bit command in
-- the high bits, and 12-bit data in the low bits.  The commands are
-- defined here.
--
CONSTANT LCMD_HIPINS = 1 ;	-- Hold high pin of DAFC and input choice
CONSTANT LCMD_MDPINS = 2 ;	-- Hold middle 12-pins of DAFC
CONSTANT LCMD_LOPINS = 3 ;	-- Load low 12-pins of DAFC, latch all outputs
CONSTANT LCMD_IFDOPT = 4 ;	-- IFD internal options

-- ------------------------------
-- Status word that is sent from IFD --> Rx following every K28.5
-- downlink framing sequence.
--
CONSTANT IFDSTSBITS  = 96 ;	-- Total number of IFD status bits sent

CONSTANT IFS_UPLINK_BERR     = 85 ;	-- Uplink bit error, cleared each sts send

CONSTANT IFS_UPLINK_OKAY     = 84 ;	-- Uplink is presently okay \
CONSTANT IFS_UPLINK_JTDO     = 83 ;	-- JTAG TDO from IFD chain   \  Do not change
CONSTANT IFS_UPLINK_JTMS     = 82 ;	-- JTAG TMS readback state    >  the location
CONSTANT IFS_UPLINK_JTDI     = 81 ;	-- JTAG TMS readback state   /  of these bits
CONSTANT IFS_UPLINK_JTCK     = 80 ;	-- JTAG TMS readback state  /

CONSTANT IFS_TEMPMON_HIB     = 55 ;	-- High/Low bits of the latest byte
CONSTANT IFS_TEMPMON_LOB     = 48 ;	--   read from the temperature monitor.

CONSTANT IFS_CODEREV_HIB     = 47 ;	-- High/Low bits of code revision level
CONSTANT IFS_CODEREV_LOB     = 40 ;	--   (8 bits)

CONSTANT IFS_BOARDREV_HIB    = 39 ;	-- High/Low bits of board etch rev
CONSTANT IFS_BOARDREV_LOB    = 36 ;	--   (4 bits)

CONSTANT IFS_BOOTMOD_HIB     = 35 ;	-- High/Low bits of boot module
CONSTANT IFS_BOOTMOD_LOB     = 33 ;	--   (3 bits)

CONSTANT IFS_BOOTREV_HIB     = 32 ;	-- High/Low bits of boot code version
CONSTANT IFS_BOOTREV_LOB     = 30 ;	--   (3 bits)

CONSTANT IFS_SERIALNUM_HIB   = 29 ;	-- High/Low bits of serial number
CONSTANT IFS_SERIALNUM_LOB   = 16 ;	--   (14 bits)

CONSTANT IFS_PLLERROR        =  3 ;	-- Clock PLL is not locked
CONSTANT IFS_NORMSW          =  2 ;	-- IFD switches are in "Normal" position
CONSTANT IFS_DIAGY           =  1 ;	-- Diagnostic "Y" bit
CONSTANT IFS_DIAGX           =  0 ;	-- Diagnostic "X" bit

-- ************************************
-- *                                  *
-- * Global Circuit Board Definitions *
-- *                                  *
-- ************************************

-- ------------------------------
-- Interrupt UNIT assignments to ISR register
--
CONSTANT RX8INTUNIT_DMA      =  0 ;	-- DMA interrupts
CONSTANT RX8INTUNIT_IQLOG    =  1 ;	-- IQ Logger
CONSTANT RX8INTUNIT_DIRIF    =  2 ;	-- Direct IF logger
CONSTANT RX8INTUNIT_TIMER0   =  3 ;	-- Counter/Timer #0
CONSTANT RX8INTUNIT_TIMER1   =  4 ;	-- Counter/Timer #1
CONSTANT RX8INTUNIT_TIMER2   =  5 ;	-- Counter/Timer #2

-- Other hardware constants
--
CONSTANT RX8CLKFREQ    = 72000000 ;	-- RVP8/Rx Reference clock frequency
CONSTANT RX8BOOTMIDCLK = 0 ;		-- Boot data transitions on edges

CONSTANT IFDCLKFREQ    = 72000000 ;	-- Similar numbers for IFD
CONSTANT IFDBOOTMIDCLK = 0 ;
