/* **********************************************************************
 * *                                                                    *
 * *            RVP8/Tx PCI Card Private Driver Definitions             *
 * *                                                                    *
 * **********************************************************************
 * File: rda/pcicards/rvp8tx_def.h
 *
 *                        COPYRIGHT (c) 2002  BY
 *          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
 * 
 * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
 * ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
 * INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
 * COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
 * OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
 * TRANSFERED.
 */
#ifndef SIGMET_RVP8TX_DEF_H
#define SIGMET_RVP8TX_DEF_H 1

/* ------------------------------
 * Opaque driver information structure
 */
struct rvp8tx_info {		
  /* Card file descriptors and memory pointers
   */
  SINT4 sizes[2] ;		/* Sizes and channels for each mapped */
  SINT4 chans[2] ;		/*   PCI or kernel memory segment. */
  volatile struct rvp8tx_csr *csr ; /* ==> Control/Status area */
  volatile struct rvp8tx_mem *mem ; /* ==> On-board shared memory */

  char sDevName[40] ;		/* Device name */

  UINT4 lOpened ;		/* Device is opened */
  UINT4 lSecUnit ;		/* Secondary unit (of possible two) */
  struct rda_boardinfo openInfo ;

  /* Diagnostic test results, and related information.
   */
  UINT4 dgBits ;		/* Summary error bits */
#define TX8DG_MIRROR    0x00000001 /* PCI mirror register */
#define TX8DG_MEM       0x00000002 /* On-board RAM */

  UINT4 dgMirrorBits[2] ;	/* PCI mirror errors (0-->1 and 1-->0 errors) */
  UINT4 dgMemBits ;		/* Memory error bits */

  /* Configuration information about the board itself, which can not
   * be deduced from the board alone, i.e., must be supplied to the
   * driver externally.
   */
  FLT4 fTxClk ;			/* On-board synthesis clock, MHz */
  FLT4 fTxOpAmpFix ;		/* AdHoc fix for frequency depencencies */

  /* State of the primary TxClk oscillator/VCXO
   */
  UINT4 lEnablePLL ;		/* PLL feedback is enabled */
  UINT4 iBtimePLLError ;	/* Time last PLL locking error was seen */

  /* Housekeeping information related to waveform generation on each
   * of the two output channels.
   */
  struct TxDACSpecs txSpecs[ 2 ] ;

  /* Information about the onboard general purpose timer(s).
   */
  struct gpTimerInfo gpTimerInfo ;

  /* All PCI access to the board's CSR registers are locked by this
   * one mutex.  Although this may sometimes lockout two unrelated
   * processes that would not actually interfere with each other, it
   * removes any worry about deadly embraces caused by order of locks
   * and order of subroutine calls.
   */
  pthread_mutex_t CSRMutex ;	/* For indivisible CSR access */

  /* Likewise, the following mutex should bracket all indivisible
   * sequences of driver activity that can not be handled by the CSR
   * lock alone.
   */
  pthread_mutex_t SeqMutex ;	/* For indivisible sequential access */
} ;

#endif /* #ifndef SIGMET_RVP8TX_DEF_H */
