/* **********************************************************************
 * *                                                                    *
 * *     Hardware Register Mappings for the RVP8/Rx Receiver Board      *
 * *                                                                    *
 * **********************************************************************
 * File: rda/pcicards/rvp8rx.h
 *
 *                        COPYRIGHT (c) 2001  BY
 *          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
 * 
 * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
 * ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
 * INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
 * COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
 * OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
 * TRANSFERED.
 */
#ifndef SIGMET_RVP8RX_H
#define SIGMET_RVP8RX_H 1

/* = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 * This file must be manually maintained in parallel with its PLD
 *   companion file: rvp8rx.inc.  The syntax between C and AHDL
 *        is too different to try to patch automatically.
 * = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 */

/* **************************************
 * *                                    *
 * * RVP8/Rx Control/Status Definitions *
 * *                                    *
 * **************************************
 */
#define RX8CSRSZ             64	/* CSR decoded address space (DWORDs) */
struct rvp8rx_csr {		
  UINT4 iReset ;		/* Write RDA_RESET_DATA ==> reset */
  UINT4 iISR ;			/* Interrupt Service Register */

  UINT4 pad02x01[0x01] ;

  /* ------------------------------
   * Board Edge LEDs.  Note that the "Always ON" code is assigned
   * the value zero so that all of the LEDs light up upon reset.
   */
  UINT4 iRedLED ;		/* Red LED options */
#define RX8REDLED_ON        0	/*   On always */
#define RX8REDLED_OFF       1	/*   Off always */
#define RX8REDLED_PCIACT    2	/*   Shows PCI access */

 UINT4 iGrnLED ;		/* Green LED options */
#define RX8GRNLED_ON        0	/*   On always */
#define RX8GRNLED_OFF       1	/*   Off always */

 UINT4 iSigLED ;		/* Green "signal detect" LED options */
#define RX8SIGLED_ON        0	/*   On always */
#define RX8SIGLED_OFF       1	/*   Off always */
#define RX8SIGLED_FIBER     2	/*   Shows downlink signal detected */

  /* ------------------------------
   * Status from the remote IFD.  The low 16 bits are two 8-bit status
   * bytes from the most recent two downlink sync receptions.  The
   * hardware keeps the last two bytes for newer IFDs that send Hi/Lo
   * status.
   */
  UINT4 iRcvr ;			/* Downlink receiver Control/Status */

  /* Older legacy RVP7 IFDs had a single status byte in the following
   * format.
   */
#define RX8RCVRL_REV0       0	/*    Revision level of data PLD. */
#define RX8RCVRL_REV1       1
#define RX8RCVRL_REV2       2
#define RX8RCVRL_REV3       3
#define RX8RCVRL_DIAGX      5	/*    DIAGX dignostic bit asserted */
#define RX8RCVRL_DIAGY      6	/*    DIAGY dignostic bit asserted */
#define RX8RCVRL_NORM       7	/*    Switches are in normal setting */

  /* The following two sets of bit definitions apply to the two
   * possible 7-bit patterns from newer RVP7 IFDs.
   */
#define RX8RCVR0_REV0       0	/*    Revision level of data PLD. */
#define RX8RCVR0_REV1       1
#define RX8RCVR0_REV2       2
#define RX8RCVR0_REV3       3
#define RX8RCVR0_DIAGX      4	/*    DIAGX dignostic bit asserted */
#define RX8RCVR0_DIAGY      5	/*    DIAGY dignostic bit asserted */
#define RX8RCVR0_NORM       6	/*    Switches are in normal setting */

#define RX8RCVR1_PLLERR     6	/*    Error in user clock PLL */

#define RX8RCVR_HIBYTE      7	/*    Which 7-bit pattern we have */

  /* The second generation RVP8 IFD was able to redefine the low
   * status bits more cleanly.
   */
#define RX8RCVR_DIAGX       0	/*    DIAGX dignostic bit asserted */
#define RX8RCVR_DIAGY       1	/*    DIAGY dignostic bit asserted */
#define RX8RCVR_NORM        2	/*    Switches are in normal setting */
#define RX8RCVR_PLLERR      3	/*    Error in user clock PLL */

  /* Remaining control and status bits are independent of the status
   * format received from the IFD.
   */
#define RX8RCVR_SIGDET     16	/*    Downlink signal detected */
#define RX8RCVR_DIRECTIF   17	/*    Output 12-bit samples directly */
#define RX8RCVR_DIAGCNT    18	/*    Diagnostic counter output */
#define RX8RCVR_NOSYNC     19	/*    Ignore RXSYNC input */
#if 0   /* --- Deleted Entries --- */
#define RX8RCVR_REQRXCLK   20	/*    Lock AQCLK2X either to downlink */
#define RX8RCVR_REQXTAL    21	/*      clock or internal crystal. */
#define RX8RCVR_STSRXCLK   22	/*    Actual selection */
#endif  /* ----------------------- */
#define RX8RCVR_UPLINKOK   23	/*    Uplink being received okay */

  /* ------------------------------
   * Manchester encoded uplink bit definitions.  The payload bits are
   * carried on top of a synchronous self-framing protocol, and consist
   * of 8-bits of data and a single Command-vs-Data flag.  Writing to
   * the CSR queues a word for delivery to the IFD; reading from the
   * CSR returns the number of used slots in the FIFO.
   */
  UINT4 iUplinkFIFO ;		/* Uplink command stream and status */

#define UPFIFO_DEPTH      512   /* Depth of PCI-->SyncTx FIFO */
#define UPFIFO_CMDBIT       8   /* Command (versus data) bit */

#define UPFIFO_KEEPALIVE 0x00   /* Inserted periodically on healthy link */
#define UPFIFO_RESET     0x01   /* Reset the entire IFD */
#define UPFIFO_BOOTCHIP  0x02   /* Command to 7064 boot chip (data follows) */
#define UPFIFO_TEMPCHIP  0x04   /* Sample temperature, low bits = <RSV,ONCHIP> */
#define UPFIFO_PLLCLK    0x08   /* LMX2306 , low bits = <CLK,DATA,LE> */
#define UPFIFO_JTAG      0xF0   /* JTAG cmd, low bits = <ENAB,TMS,TDI,TCK> */

  /* ------------------------------
   * System time register, counts in units of the acquisition clock.
   * The low four bits are zeroed, thereby giving a PCI resolution of
   * approx one half microsecond.
   */
  UINT4 iSysTime ;		/* Read-only time */

  /* ------------------------------
   * (I,Q) Data Logger Registers
   */
  UINT4 iqLoggerCSR ;		/* Control/Status */
#define RX8IQLCSR_RUNREQ    0	/*   Request to run (I,Q) logger */
#define RX8IQLCSR_RUNNING   1	/*   Logger is running now */
#define RX8IQLCSR_IQHCLR    2	/*   Clear IQHEAD register */
#define RX8IQLCSR_PULCLR    3	/*   Clear PULSES register */
#define RX8IQLCSR_NOWRAP    4	/*   Kill RUNREQ on Data/Hdr wrap */

  UINT4 iqWrapHead ;		/* (I,Q) wrap/head ptr (read-only) */
#define IQWH_HEAD( VAL ) ( (VAL)        & 0x7FFFF)
#define IQWH_WRAP( VAL ) (((VAL) >> 20) & 0x0000F)

  UINT4 iPulseCount ;		/* Pulse counter (read-only) */
#define RX8PULCNTHIB       15	/*   High bit of counter */

  /* ------------------------------
   * Local side configuration of DMA transfers.
   */
  UINT4 iDMACSR ;		/* Control/Status */
#define RX8DMACSR_RUNREQ    0	/*   Fill FIFO from MPM reads */

  UINT4 iDMAddr ;		/* DMA read address from MPM */

  /* ------------------------------
   * Front panel connector I/O and signal assignments
   */
  UINT4 iPanel ;		/* Control/Status */
#define RX8PANEL_TG0SEL     0	/*   Trigger 0, or Polar 0 */
#define RX8PANEL_TG1SEL     1	/*   Trigger 1, or Polar 1 */

  UINT4 pad0Fx01[0x01] ;

  /* ------------------------------
   * Extended IFD status.  These additional status bits are sent down
   * from the IFD on each K28.5 framing cycle.
   */
  UINT4 iIFDSts[4] ;

  /* ------------------------------
   * Bit-Error-Rate monitors for three downlink channels and one
   * uplink channel.  These four 8-bit counters will max out at 0xFF,
   * and are cleared every time they are read.
   */
  UINT4 iBerr ;			/* <UpLink , Rx-C , Rx-B , Rx-A> */

  /* ------------------------------
   * DSP/FIR Filter Control (Rev.C and higher boards)
   */
  UINT4 iDSPCSR ;		/* Control/Status */
#define RX8DSPCSR_RUNREQ    0	/*   Request to run FIR filters */
#define RX8DSPCSR_DIAGCNT   1	/*   Apply diagnostic counter input */
#define RX8DSPCSR_LOWSUM    2 	/*   Shift output to get LSBs exactly */

#define RX8DSPCSR_NVECS0    4	/*   Number of (I,Q) vecs (minus 1) */
#define RX8DSPCSR_NVECS1    5	/*     generated per range bin. */

#define RX8DSPCSR_DCMATE0   8	/*   Decimation factor (minus 2) */
#define RX8DSPCSR_DCMATE1   9
#define RX8DSPCSR_DCMATE2  10
#define RX8DSPCSR_DCMATE3  11
#define RX8DSPCSR_DCMATE4  12
#define RX8DSPCSR_DCMATE5  13

#define RX8DSPCSR_NDSPS0   16	/* Number of DSPs for which this */
#define RX8DSPCSR_NDSPS1   17	/*   FPGA has been compiled. */
#define RX8DSPCSR_NDSPS2   18
#define RX8DSPCSR_NDSPS3   19

  /* The coefficient lookup tables are write-only from the PCI side.  They
   * are written one word at a time from this address:
   *
   *    [ 31..24 ] : Which RAM bank to write (for multiplier 0, 1, 2, etc)
   *    [ 23..16 ] : 8-bit address within the selected coefficient RAM
   *    [ 15.. 0 ] : 16-bit signed coefficient value
   *
   * The 8-bit coefficient addresses are organized as follows:
   *
   *    [    7 ] : Selects First/Second set of 4x clocked decimation registers
   *    [ 6..0 ] :          0 -->   DECIMATE-1  Coefficients for I of first vector
   *                 DECIMATE --> 2*DECIMATE-1  Coefficients for Q of first vector
   *               2*DECIMATE --> 3*DECIMATE-1  Coefficients for I of second vector
   *               3*DECIMATE --> 4*DECIMATE-1  Coefficients for Q of secton vector
   *                                            etc, according to number of vectors
   */
  UINT4 iDSPCoef ;		/* Coefficient registers (write only) */
#define RX8DSPCOEF_WILDB  0xFF	/*   Wild card bank (all banks written) */

  UINT4 pad17x09[0x09] ;

  /* ------------------------------
   * Front Panel Display Control
   */
  UINT4 iFpdCSR ;		/* Control/Status */
  UINT4 iFpdData ;		/* Direct character read/write */

  /* ------------------------------
   * Trigger Generator Control
   */
  UINT4 iTgCSR ;		/* Control/Status */
#define RX8TGCSR_RUNREQ     0	/*   Request to begin running */
#define RX8TGCSR_RUNNING    1	/*   Real time mode is running (RD-Only) */
#define RX8TGCSR_HEAPREQ    2	/*   Requested Hi/Lo memory heap */
#define RX8TGCSR_CURHEAP    3	/*   Memory heap currently in use (RD-Only) */
#define RX8TGCSR_DFBANK0    4	/*   Requested bank of waveforms */
#define RX8TGCSR_DFBANK1    5
#define RX8TGCSR_DFBANK2    6
#define RX8TGCSR_DFBANK3    7
#define RX8TGCSR_DFBANK4    8
#define RX8TGCSR_DFBANK5    9
#define RX8TGCSR_EXTERN    12	/*   Use external trigger source */
#define RX8TGCSR_XSYNCH    13	/*   Allow synchronous trig lineup */
#define RX8TGCSR_RISING    14	/*   Use rising edge of trigger */
#define RX8TGCSR_TIMEOUT   15	/*   Missing external trigger (RD-Only) */
#define RX8TGCSR_TOBANK    16	/*   Running with timeout bank (RD-Only) */
#define RX8TGCSR_RESETREQ  17	/*   Reset the trig generator (WR-Only) */
#define RX8TGCSR_PENDING   18	/*   Pending/Busy with TGNEW... (RD-Only) */
#define RX8TGCSR_SNAPPED   19	/*   Wr1->Set, Rd: TGNEW... bits accepted */
#define RX8TGCSR_TGNEW     20	/*   Request to begin new Bank/Heap */
#define RX8TGCSR_TGNEWGP0  21	/*   Requests to begin new Bank/Heap */
#define RX8TGCSR_TGNEWGP1  22	/*     when the corresponding GPTimer */
#define RX8TGCSR_TGNEWGP2  23	/*     fires an interrupt. */
#define RX8TGCSR_PHASELO   24	/*   Bits of Tx phase for the first */
#define RX8TGCSR_PHASEHI   31	/*     pulse of newly starting bank. */

  /* ------------------------------
   * IFD Uplink Transmitter Control
   */
  UINT4 iUplinkCSR ;		/* Control/Status */
#define RX8UPCSR_RUNREQ     0	/*   Run from burst triggers */
#define RX8UPCSR_SENDING    1	/*   Transmitter is running now */
#define RX8UPCSR_HEAPREQ    2	/*   Request and Current Selection */
#define RX8UPCSR_HEAPSEL    3	/*     of Hi/Lo memory heap. */
#define RX8UPCSR_DIAGX      4	/*   IFD diagnostic bits */
#define RX8UPCSR_DIAGY      5
#define RX8UPCSR_LEDON      6   /*   IFD Green LED On, or Off, or */
#define RX8UPCSR_LEDOFF     7	/*     follow downlink signal detect. */
#define RX8UPCSR_SINGLE     8	/*   Generate a single transmission */
#define RX8UPCSR_IFDRESET   9	/*   Reset the remote IFD */

  /* The 16-bit words can optionally be interpreted as a 4-bit command
   * in the high bits, and 12-bit data in the low bits.  The commands
   * are defined here.
   */
#define LCMD_HIPINS  1		/* Hold high pin of DAFC and input choice */
#define LCMD_MDPINS  2		/* Hold middle 12-pins of DAFC */
#define LCMD_LOPINS  3		/* Load low 12-pins of DAFC, latch all outputs */
#define LCMD_IFDOPT  4		/* IFD internal options */

  /* ------------------------------
   * Direct IF data sample storage.
   */
  UINT4 iDIFCSR ;		/* Control/Status */
#define RX8DIFCSR_WRCONT    0	/*   Continuous IF recording */
#define RX8DIFCSR_NOWAIT    1	/*   Don't wait for start of pulse */
#define RX8DIFCSR_WTBANK    2	/*   If waiting, then also wait for BANK */
#define RX8DIFCSR_BANK0     4	/*   Trigger bank to wait for */
#define RX8DIFCSR_BANK1     5
#define RX8DIFCSR_BANK2     6
#define RX8DIFCSR_BANK3     7
#define RX8DIFCSR_BANK4     8
#define RX8DIFCSR_BANK5     9

  UINT4 iDIFPulseCnt ;		/* Desired pulse count */
#define RX8DIFMAXP        255	/*   Maximum pulse count */

  UINT4 iDIFAddress ;		/* Write address within DIF buffer */

  /* ------------------------------
   * Trigger blanking control.  The low bits (WR-Only) select which of
   * the USER triggers are affected by the blanking request.
   */
  UINT4 iTgBlnk ;		/* Control/Status */
#define RX8TGBLNK_REQ      30 	/*   Request to blank triggers */
#define RX8TGBLNK_ACK      31 	/*   Triggers are blanked now (RD-Only) */

  /* ------------------------------
   * Range mask generation
   */
  UINT4 iRngCSR ;		/* Control/Status */
#define RX8RNGCSR_RUNREQ    0	/*   Request to begin running */
#define RX8RNGCSR_RUNNING   1	/*   Real time mode is running */

  /* ------------------------------
   * FIR Filter Control
   */
  UINT4 iFirCSR ;		/* Control/Status */
#define RX8FIRCSR_RUNREQ    0	/*   Request to run FIR filters */
#define RX8FIRCSR_YDIV16    1	/*   Divide Y output data by 16 */
#define RX8FIRCSR_XOUTZER   2	/*   Zero the X filter outputs */
#define RX8FIRCSR_YOUTZER   3	/*   Zero the Y filter outputs */

#define RX8FIRCSR_XIDAT16   4	/*   X:DAT<15..4> (IF data hi bits) */
#define RX8FIRCSR_XICNT16   5	/*   X:CNT<15..4> (Counter hi bits) */
#define RX8FIRCSR_XICNT12   6	/*   X:CNT<11..0> (Counter lo bits) */

#define RX8FIRCSR_YIDAT04   8	/*   Y:(0,0,0,0,0,0,0,0, DAT<3..0>) */
#define RX8FIRCSR_YICNT04   9	/*   Y:(0,0,0,0,0,0,0,0, CNT<3..0>) */
#define RX8FIRCSR_YICNT12  10	/*   Y: CNT<11..0> (Counter lo bits) */
#define RX8FIRCSR_YICSCAD  11	/*   Y:ROUT<11..0> (Cascade from X) */

#define RX8FIRCSR_DCMATE0  12	/*   Decimation factor (minus 2) */
#define RX8FIRCSR_DCMATE1  13
#define RX8FIRCSR_DCMATE2  14
#define RX8FIRCSR_DCMATE3  15

#define RX8FIRCSR_NCHIPS0  16	/*   Number of filter chips (exactly) */
#define RX8FIRCSR_NCHIPS1  17	/*     contributing to the output sum. */

#define RX8FIRCSR_NVECS0   18	/*   Number of (I,Q) vecs (minus 1) */
#define RX8FIRCSR_NVECS1   19	/*     generated per range bin. */

#define RX8FIRCSR_ALLIO  ( BIT(RX8FIRCSR_XIDAT16) | BIT(RX8FIRCSR_XICNT16) | \
  BIT(RX8FIRCSR_XICNT12) | BIT(RX8FIRCSR_YIDAT04) | BIT(RX8FIRCSR_YICNT04) | \
  BIT(RX8FIRCSR_YICNT12) | BIT(RX8FIRCSR_YICSCAD) | BIT(RX8FIRCSR_YDIV16 ) )

  UINT4 iLFData ;		/* LF3320's "LF" interface, data */

  UINT4 iLFCtrl ;		/* LF3320's "LF" interface, control */
#define RX8LFCTRL_XLDA     0	/*   X filter, A channel */
#define RX8LFCTRL_XLDB     1	/*   X filter, B channel */
#define RX8LFCTRL_YLDA     2	/*   Y filter, A channel */
#define RX8LFCTRL_YLDB     3	/*   Y filter, B channel */
#define RX8LFCTRL_CHIP0    4	/*   Enable writing for the three */
#define RX8LFCTRL_CHIP1    5	/*     sets of LF3320 chips. */
#define RX8LFCTRL_CHIP2    6

  /* ------------------------------
   * FIR Output Data Word Packer
   */
  UINT4 iqPackerCSR ;		/* Control/Status */
#define RX8IQPCSR_RUNREQ    0	/*   Request to run data packing */
#define RX8IQPCSR_DIRECT    1	/*   Direct copy of 32-bit FIR values */

  /* ------------------------------
   * General purpose Counter/Timers
   */
#define RX8NTIMERS          3	 /* Number of timers onboard */
  UINT4 iTimerCSRs[RX8NTIMERS] ; /* Control/Status for each timer */
#define RX8TIMER0_NBITS    24	 /* Number of bits in each counter/timer */
#define RX8TIMER1_NBITS    12
#define RX8TIMER2_NBITS    12

  UINT4 pad30x0E[0x0E] ;

  /* ------------------------------
   * PCI Read/Write 32-bit diagnostic mirror
   */
  UINT4 iPCIMirror ;		/* Reads back what's written */

  /* ------------------------------
   * Softplane common control/status register.  Bit definitions can be
   * found in pcicards_lib.h.
   */
  UINT4 iSPLCom ;
} ;

/* ************************************
 * *                                  *
 * * RVP8/Rx Master FPGA Memory Block *
 * *                                  *
 * ************************************
 */
#define RX8MASTERSZ_AB 0x080000	/* Memory size (512K DWORDs) for */
#define RX8MASTERSZ    0x100000	/*   different revision boards. */

#define RX8IQLMEM      0x000000	/* (I,Q) logger base address */
#define RX8IQLSIZE     0x070000	/*   and size. */

#define RX8PHDRMEM     0x070000	/* Pulse header table base */
#define RX8PHDRSIZE    0x004000	/*   address and size. */

struct rvp8rx_master {
  /* The (I,Q) memory heap is used by the data logger to hold packed
   * data samples.  These are addressed by the iqHead register, which
   * points to where the next item will be written.
   */
  UINT4 iqlHeapMem[ RX8IQLSIZE ] ;

  /* The array of pulse headers holds the history of pulses that have
   * come in so far.
   */
  UINT4 pad_1[ RX8PHDRMEM - (RX8IQLMEM + RX8IQLSIZE) ] ;

#define RX8NPHEADERS (RX8PHDRSIZE / RX8PHDRWORDS)
  struct rvp8rx_pulseHeader pulseHeaders[ RX8NPHEADERS ] ;
} ;

/* ************************************
 * *                                  *
 * * RVP8/Rx Filter FPGA Memory Block *
 * *                                  *
 * ************************************
 */
#define RX8FILTERSZ_AB 0x080000	/* Memory size (512K DWORDs) for */
#define RX8FILTERSZ    0x100000	/*   different revision boards. */

#define RX8LINKMEM     0x000100	/* IFD uplink transmitter memory */
#define RX8LINKSIZE    0x000020	/*   and size. */

#define RX8RNGMEM      0x004000	/* Range mask data pattern memory */
#define RX8RNGSIZE     0x004000	/*   and size. */

                                /* Hole: ( 0x08000 - 0x0FFFF ) */

#define RX8DIFMEM      0x010000	/* Direct IF data sample memory */
#define RX8DIFSIZE     0x010000	/*   and size. */
  #define RX8DIFMAGIC    0x03BF	/* Magic number at start of each pulse */

#define RX8TGDMEM      0x040000	/* Trigger generator memory */
#define RX8TGDSIZE     0x040000	/*   and size. */

  /* Opcodes in pulse descriptor words.  These are located in low
   * memory for the start of each sequence, as well as within the
   * sequences * themselves for each new pulse.
   */
  #define RX8TGADRHIB       16	/* High bit of address field */
  #define RX8TGWAVEINC      17	/* "Increment waveform" opcode bit */
  #define RX8TGINTABLE      18	/* "Interruptible" opcode bit */
  #define RX8TGPHASELO      24	/* Low and high bits of Tx phase */
  #define RX8TGPHASEHI      31

  /* Opcodes in pattern control words within each pulse
   */
  #define RX8TGCNTHIB       15	/* High bit of iteration count field */
  #define RX8TGDATA         16	/* "Data" vs "Hold" opcode bit */
  #define RX8TGCONT         17	/* "Continue" opcode bit */

struct rvp8rx_filter {
  /* The uplink transmitter memory is divided into two independent
   * heaps.  This allows new serial data words to be loaded without
   * interfering with the timing at all.
   */
  UINT4 pad_1[ RX8LINKMEM ] ;
  UINT4 iLinkMem[2][ RX8LINKSIZE/2 ] ;

  /* The range mask generator consists of a bit mask at the resolution
   * of the AQCLK acquisition clock.  Setting a bit in this table will
   * cause an (I,Q) sample to be acquired, with pipelining of the FIR
   * beginning at that precise range.
   */
  UINT4 pad_2[ RX8RNGMEM - (RX8LINKMEM + RX8LINKSIZE) ] ;
  UINT4 iRngMem[ RX8RNGSIZE ] ;

  /* Direct IF data samples are stored in a linear buffer.  There can
   * be data from several different pulses here.
   */
  UINT4 pad_3[ RX8DIFMEM - (RX8RNGMEM + RX8RNGSIZE) ] ;
  UINT4 iDIFMem[ RX8DIFSIZE ] ;

  /* The trigger generator memory is divided into two independent
   * heaps.  This allows new waveforms to be loaded and run without
   * interfering with the timing at all.
   */
  UINT4 pad_4[ RX8TGDMEM - (RX8DIFMEM + RX8DIFSIZE) ] ;
  UINT4 iTGMem[2][ RX8TGDSIZE/2 ] ;
} ;

/* ************************************
 * *                                  *
 * * Global Circuit Board Definitions *
 * *                                  *
 * ************************************
 */

/* ------------------------------
 * Interrupt UNIT assignments to IOR Mail Box register
 */
#define RX8INTUNIT_DMA     0	/*  DMA interrupts */
#define RX8INTUNIT_IQLOG   1	/*  IQ Logger */
#define RX8INTUNIT_DIRIF   2	/*  Direct IF logger */
#define RX8INTUNIT_TIMER0  3	/*  Counter/Timer #0 */
#define RX8INTUNIT_TIMER1  4	/*  Counter/Timer #1 */
#define RX8INTUNIT_TIMER2  5	/*  Counter/Timer #2 */

#endif /* #ifndef SIGMET_RVP8RX_H */
