-- **********************************************************************
-- *                                                                    *
-- *     Hardware Register Mappings for the RVP8/Rx Receiver Board      *
-- *                                                                    *
-- **********************************************************************
-- File: rda/pcicards/rvp8rx.inc
--
--                        COPYRIGHT (c) 2001  BY
--          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
-- 
-- THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
-- ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
-- INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
-- COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
-- OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
-- TRANSFERED.
--

-- = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-- This file must be manually maintained in parallel with its C
--   companion file: rvp8rx.h.  The syntax between C and AHDL
--        is too different to try to patch automatically.
-- = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

-- **************************************
-- *                                    *
-- * RVP8/Rx Control/Status Definitions *
-- *                                    *
-- **************************************

CONSTANT RX8CSRSZ             = 64 ;	-- CSR decoded address space (DWORDs)
CONSTANT RX8CSRHIB = LOG2(RX8CSRSZ) - 1 ;

-- ------------------------------
-- CAUTION: Address 0x00 is RESETADDR
-- CAUTION: Address 0x01 is ISR_ADDR

-- ------------------------------
-- Board Edge LEDs.  Note that the "Always ON" code is assigned the
-- value zero so that all of the LEDs light up upon reset.
--
CONSTANT RX8REDLED       = H"03" ;	-- Red LED options
  CONSTANT RX8REDLED_ON      = 0 ; 	--   On always
  CONSTANT RX8REDLED_OFF     = 1 ;	--   Off always
  CONSTANT RX8REDLED_PCIACT  = 2 ;	--   Shows PCI access

CONSTANT RX8GRNLED       = H"04" ;	-- Green LED options
  CONSTANT RX8GRNLED_ON      = 0 ; 	--   On always
  CONSTANT RX8GRNLED_OFF     = 1 ;	--   Off always

CONSTANT RX8SIGLED       = H"05" ;	-- Green "signal detect" LED options
  CONSTANT RX8SIGLED_ON      = 0 ; 	--   On always
  CONSTANT RX8SIGLED_OFF     = 1 ;	--   Off always
  CONSTANT RX8SIGLED_FIBER   = 2 ;	--   Shows fiber present

-- ------------------------------
-- Control/Status from the remote IFD.
--
CONSTANT RX8RCVR         = H"06" ;	-- Status of the receiver box
  -- The low 16 bits are two 8-bit status bytes from the most recent two
  -- downlink sync receptions.  The hardware keeps the last two bytes for
  -- newer IFDs that send Hi/Lo status
  --
  CONSTANT RX8RCVR_SIGDET    = 16 ;	--   Fiber signal detected
  CONSTANT RX8RCVR_DIRECTIF  = 17 ;	--   Output 12-bit samples directly
  CONSTANT RX8RCVR_DIAGCNT   = 18 ;	--   Diagnostic counter output
  CONSTANT RX8RCVR_NOSYNC    = 19 ;	--   Ignore RXSYNC input
  CONSTANT RX8RCVR_REQRXCLK  = 20 ;	--   Request to lock AQCLK2X to downlink
  CONSTANT RX8RCVR_REQXTAL   = 21 ;	--     clock or internal crystal.
  CONSTANT RX8RCVR_STSRXCLK  = 22 ;	--   Actual selection
  CONSTANT RX8RCVR_UPLINKOK  = 23 ;	--   Uplink being received okay

-- ------------------------------
-- System time register, counts in units of the acquisition clock.  The
-- low four bits are zeroed, thereby giving a PCI resolution of approx
-- one half microsecond.
--
CONSTANT RX8SYSTIME      = H"08" ;	-- Read-only time

-- ------------------------------
-- (I,Q) Data Logger Registers
--
CONSTANT RX8IQLCSR       = H"09" ;	-- Control/Status
  CONSTANT RX8IQLCSR_RUNREQ  = 0 ;	--   Request to run (I,Q) logger
  CONSTANT RX8IQLCSR_RUNNING = 1 ;	--   Logger is running now
  CONSTANT RX8IQLCSR_IQHCLR  = 2 ;	--   Clear IQHEAD register
  CONSTANT RX8IQLCSR_PULCLR  = 3 ;	--   Clear PULSES register
  CONSTANT RX8IQLCSR_NOWRAP  = 4 ;	--   Kill RUNREQ on Data/Hdr wrap

CONSTANT RX8IQHEAD       = H"0A" ;	-- (I,Q) write ptr (read-only)

CONSTANT RX8PULCNT       = H"0B" ;	-- Pulse counter (read-only)
  CONSTANT RX8PULCNTHIB      = 15 ;	--   High bit of counter

-- ------------------------------
-- Local side configuration of DMA transfers.
--
CONSTANT RX8DMACSR       = H"0C" ;	-- Control/Status
  CONSTANT RX8DMACSR_RUNREQ  = 0 ;	--   Fill FIFO from MPM reads

CONSTANT RX8DMADDR       = H"0D" ;	-- DMA read address from MPM

-- ------------------------------
-- Front panel connector I/O and signal assignments
--
CONSTANT RX8PANEL        = H"0E" ;	-- Control/Status
  CONSTANT RX8PANEL_TG0SEL   = 0 ;	--   Trigger 0, or Polar 0
  CONSTANT RX8PANEL_TG1SEL   = 1 ;	--   Trigger 1, or Polar 1

--  - - - - - - - - - - - - - - - - - - - -
--  -  Start of Filter FPGA Decoded Area  -
--  - - - - - - - - - - - - - - - - - - - -

-- ------------------------------
-- Front Panel Display Control
--
CONSTANT RX8FPDCSR       = H"20" ;	-- Control/Status
CONSTANT RX8FPDATA       = H"21" ;	-- Character read/write

-- ------------------------------
-- Trigger Generator
--
CONSTANT RX8TGCSR        = H"22" ;	-- Control/Status
  CONSTANT RX8TGCSR_RUNREQ   =  0 ;	--   Request to begin running
  CONSTANT RX8TGCSR_RUNNING  =  1 ;	--   Real time mode is running (RD-Only)
  CONSTANT RX8TGCSR_HEAPREQ  =  2 ;	--   Requested Hi/Lo memory heap
  CONSTANT RX8TGCSR_CURHEAP  =  3 ;	--   Memory heap currently in use (RD-Only)
  CONSTANT RX8TGCSR_DFBANK0  =  4 ;	--   Requested bank of waveforms
  CONSTANT RX8TGCSR_DFBANK1  =  5 ;
  CONSTANT RX8TGCSR_DFBANK2  =  6 ;
  CONSTANT RX8TGCSR_DFBANK3  =  7 ;
  CONSTANT RX8TGCSR_DFBANK4  =  8 ;
  CONSTANT RX8TGCSR_DFBANK5  =  9 ;
  CONSTANT RX8TGCSR_EXTERN   = 12 ;	--   Use external trigger source
  CONSTANT RX8TGCSR_XSYNCH   = 13 ;	--   Allow synchronous trig lineup
  CONSTANT RX8TGCSR_RISING   = 14 ;	--   Use rising edge of trigger
  CONSTANT RX8TGCSR_TIMEOUT  = 15 ;	--   Missing external trigger (RD-Only)
  CONSTANT RX8TGCSR_TOBANK   = 16 ;	--   Running with timeout bank (RD-Only)
  CONSTANT RX8TGCSR_RESETREQ = 17 ;	--   Reset the trig generator (WR-Only)
  CONSTANT RX8TGCSR_PENDING  = 18 ;	--   Pending/Busy with TGNEW... (RD-Only)
  CONSTANT RX8TGCSR_SNAPPED  = 19 ;	--   Wr1->Set, Rd: TGNEW... bits accepted
  CONSTANT RX8TGCSR_TGNEW    = 20 ;	--   Request to begin new Bank/Heap
  CONSTANT RX8TGCSR_TGNEWGP0 = 21 ;	--   Requests to begin new Bank/Heap
  CONSTANT RX8TGCSR_TGNEWGP1 = 22 ;	--     when the corresponding GPTimer
  CONSTANT RX8TGCSR_TGNEWGP2 = 23 ;	--     fires an interrupt.
  CONSTANT RX8TGCSR_PHASELO  = 24 ;	--   Bits of Tx phase for the first
  CONSTANT RX8TGCSR_PHASEHI  = 31 ;	--     pulse of newly starting bank.

-- ------------------------------
-- Serial Uplink to the IFD
--
CONSTANT RX8UPCSR        = H"23" ;	-- Control/Status
  CONSTANT RX8UPCSR_RUNREQ   =  0 ;	--   Run from burst triggers
  CONSTANT RX8UPCSR_SENDING  =  1 ;	--   Transmitter is running now
  CONSTANT RX8UPCSR_HEAPREQ  =  2 ;	--   Request and Current Selection
  CONSTANT RX8UPCSR_HEAPSEL  =  3 ;	--     of Hi/Lo memory heap.
  CONSTANT RX8UPCSR_DIAGX    =  4 ;	--   IFD diagnostic bits
  CONSTANT RX8UPCSR_DIAGY    =  5 ;
  CONSTANT RX8UPCSR_LEDON    =  6 ;	--   IFD Green LED On, or Off, or
  CONSTANT RX8UPCSR_LEDOFF   =  7 ;	--     follow fiber signal detect.
  CONSTANT RX8UPCSR_SINGLE   =  8 ;	--   Generate a single transmission
  CONSTANT RX8UPCSR_IFDRESET =  9 ;	--   Reset the remote IFD

  -- Constants defining serial uplink bit times for the standard uplink
  -- format.
  --
  CONSTANT LBIT_START  =  0 ;	-- The "start" bit that ends the burst
  CONSTANT LBIT_CHK0HI =  1 ;	-- Noise immunity check bits
  CONSTANT LBIT_CHK1HI =  2 ;
  CONSTANT LBIT_CHK2LO =  3 ;
  CONSTANT LBIT_AFC15  =  4 ;	-- Bits of serial AFC code
  CONSTANT LBIT_AFC14  =  5 ;
  CONSTANT LBIT_AFC13  =  6 ;
  CONSTANT LBIT_AFC12  =  7 ;
  CONSTANT LBIT_AFC11  =  8 ;
  CONSTANT LBIT_AFC10  =  9 ;
  CONSTANT LBIT_AFC9   = 10 ;
  CONSTANT LBIT_AFC8   = 11 ;
  CONSTANT LBIT_AFC7   = 12 ;
  CONSTANT LBIT_AFC6   = 13 ;
  CONSTANT LBIT_AFC5   = 14 ;
  CONSTANT LBIT_AFC4   = 15 ;
  CONSTANT LBIT_AFC3   = 16 ;
  CONSTANT LBIT_AFC2   = 17 ;
  CONSTANT LBIT_AFC1   = 18 ;
  CONSTANT LBIT_AFC0   = 19 ;
  CONSTANT LBIT_RESET  = 20 ;	-- Full reset request
  CONSTANT LBIT_CMDATA = 21 ;	-- Command/Data
  CONSTANT LBIT_DIAGX  = 22 ;	-- Diagnostic bits
  CONSTANT LBIT_DIAGY  = 23 ;
  CONSTANT LBIT_LED    = 24 ;
  CONSTANT LBIT_DONE   = 25 ;	-- All done

  -- The 16-bit words can optionally be interpreted as a 4-bit command in
  -- the high bits, and 12-bit data in the low bits.  The commands are
  -- defined here.
  --
  CONSTANT LCMD_HIPINS = 1 ;	-- Hold high pin of DAFC and input choice
  CONSTANT LCMD_MDPINS = 2 ;	-- Hold middle 12-pins of DAFC
  CONSTANT LCMD_LOPINS = 3 ;	-- Load low 12-pins of DAFC, latch all outputs
  CONSTANT LCMD_IFDOPT = 4 ;	-- IFD internal options

-- ------------------------------
-- Direct IF data sample storage.
--
CONSTANT RX8DIFCSR       = H"24" ;	-- Control/Status
  CONSTANT RX8DIFCSR_WRCONT  =  0 ;	--   Continuous IF recording
  CONSTANT RX8DIFCSR_NOWAIT  =  1 ;	--   Don't wait for start of pulse
  CONSTANT RX8DIFCSR_WTBANK  =  2 ;	--   If waiting, then also wait for BANK
  CONSTANT RX8DIFCSR_BANK0   =  4 ;	--   Trigger bank to wait for
  CONSTANT RX8DIFCSR_BANK1   =  5 ;
  CONSTANT RX8DIFCSR_BANK2   =  6 ;
  CONSTANT RX8DIFCSR_BANK3   =  7 ;
  CONSTANT RX8DIFCSR_BANK4   =  8 ;
  CONSTANT RX8DIFCSR_BANK5   =  9 ;

CONSTANT RX8DIFPCNT      = H"25" ;	-- Desired pulse count
CONSTANT RX8DIFADDR      = H"26" ;	-- IF data write address
  CONSTANT RX8DIFMAXP = 255 ;		-- Maximum pulse count

-- ------------------------------
-- Trigger blanking control.  The low bits (WR-Only) select which of the
-- USER triggers are affected by the blanking request.
--
CONSTANT RX8TGBLNK       = H"27" ;	-- Control/Status
  CONSTANT RX8TGBLNK_REQ     = 30 ;	--   Request to blank triggers
  CONSTANT RX8TGBLNK_ACK     = 31 ;	--   Triggers are blanked now (RD-Only)

-- ------------------------------
-- Range mask generation
--
CONSTANT RX8RNGCSR       = H"28" ;	-- Control/Status
  CONSTANT RX8RNGCSR_RUNREQ  =  0 ;	--   Request to begin running
  CONSTANT RX8RNGCSR_RUNNING =  1 ;	--   Real time mode is running

-- ------------------------------
-- FIR Filter Control
--
CONSTANT RX8FIRCSR       = H"29" ;	-- Control/Status
  CONSTANT RX8FIRCSR_RUNREQ  =  0 ;	--   Request to run FIR filters
  CONSTANT RX8FIRCSR_YDIV16  =  1 ;	--   Divide Y output data by 16
  CONSTANT RX8FIRCSR_XOUTZER =  2 ;	--   Zero the X filter outputs
  CONSTANT RX8FIRCSR_YOUTZER =  3 ;	--   Zero the Y filter outputs

  CONSTANT RX8FIRCSR_XIDAT16 =  4 ;	--   X:DAT<15..4> (IF data hi bits)
  CONSTANT RX8FIRCSR_XICNT16 =  5 ;	--   X:CNT<15..4> (Counter hi bits)
  CONSTANT RX8FIRCSR_XICNT12 =  6 ;	--   X:CNT<11..0> (Counter lo bits)

  CONSTANT RX8FIRCSR_YIDAT04 =  8 ;	--   Y:(0,0,0,0,0,0,0,0, DAT<3..0>)
  CONSTANT RX8FIRCSR_YICNT04 =  9 ;	--   Y:(0,0,0,0,0,0,0,0, CNT<3..0>)
  CONSTANT RX8FIRCSR_YICNT12 = 10 ;	--   Y: CNT<11..0> (Counter lo bits)
  CONSTANT RX8FIRCSR_YICSCAD = 11 ;	--   Y:ROUT<11..0> (Cascade from X)

  CONSTANT RX8FIRCSR_DCMATE0 = 12 ;	--   Decimation factor (minus 2)
  CONSTANT RX8FIRCSR_DCMATE1 = 13 ;
  CONSTANT RX8FIRCSR_DCMATE2 = 14 ;
  CONSTANT RX8FIRCSR_DCMATE3 = 15 ;

  CONSTANT RX8FIRCSR_NCHIPS0 = 16 ;	--   Number of filter chips (exactly)
  CONSTANT RX8FIRCSR_NCHIPS1 = 17 ;	--     contributing to the output sum.

  CONSTANT RX8FIRCSR_NVECS0  = 18 ;	--   Number of (I,Q) vecs (minus 1)
  CONSTANT RX8FIRCSR_NVECS1  = 19 ;	--     generated per range bin.

CONSTANT RX8LFDATA       = H"2A" ;	-- LF3320's "LF" interface, data

CONSTANT RX8LFCTRL       = H"2B" ;	-- LF3320's "LF" interface, control
  CONSTANT RX8LFCTRL_XLDA    = 0 ;	--   X filter, A channel
  CONSTANT RX8LFCTRL_XLDB    = 1 ;	--   X filter, B channel
  CONSTANT RX8LFCTRL_YLDA    = 2 ;	--   Y filter, A channel
  CONSTANT RX8LFCTRL_YLDB    = 3 ;	--   Y filter, B channel
  CONSTANT RX8LFCTRL_CHIP0   = 4 ;	--   Enable writing for the three
  CONSTANT RX8LFCTRL_CHIP1   = 5 ;	--     sets of LF3320 chips.
  CONSTANT RX8LFCTRL_CHIP2   = 6 ;

-- ------------------------------
-- FIR Output Data Word Packer
--
CONSTANT RX8IQPCSR       = H"2C" ;	-- Control/Status
  CONSTANT RX8IQPCSR_RUNREQ  =  0 ;	--   Request to run data packing
  CONSTANT RX8IQPCSR_DIRECT  =  1 ;	--   Direct copy of 32-bit FIR values

-- ------------------------------
-- General purpose Counter/Timers
--
CONSTANT RX8TIMER0       = H"2D" ;	-- Timers 0-2 Control/Status
CONSTANT RX8TIMER1       = H"2E" ;
CONSTANT RX8TIMER2       = H"2F" ;

  CONSTANT RX8TIMER0_NBITS   = 24 ;	-- Number of bits in timers 0-2
  CONSTANT RX8TIMER1_NBITS   = 12 ;
  CONSTANT RX8TIMER2_NBITS   = 12 ;
					-- Timer clock sources
  CONSTANT RX8TIMER_CLK1MHZ  =  0 ;	--   1MHz (Timer #0 only)
  CONSTANT RX8TIMER_CLK1KHZ  =  0 ;	--   1KHz (Timers #1 & #2)
  CONSTANT RX8TIMER_CLKTRIG  =  1 ;	--   Trigger pulses (all timers)
  CONSTANT RX8TIMER_CLKIOSHR =  2 ;	--   I/O-62 shared (Line #N -> Timer #N)

-- ------------------------------
-- PCI Read/Write 32-bit diagnostic mirror
--
CONSTANT RX8MIRROR       = H"3E" ;	-- Reads back what's written

-- ------------------------------
-- Softplane common control/status register.  Bit definitions can be
-- found in rda_modules.inc.
--
CONSTANT RX8SPLCOM       = H"3F" ;

-- ************************************
-- *                                  *
-- * RVP8/Rx Master FPGA Memory Block *
-- *                                  *
-- ************************************

CONSTANT RX8MASTERSZ     = H"80000" ;	-- Memory size (512K DWORDs)
CONSTANT RX8MASTERHIB = LOG2(RX8MASTERSZ) - 1 ;

CONSTANT RX8IQLMEM       = H"00000" ;	-- (I,Q) logger base address
CONSTANT RX8IQLSIZE      = H"70000" ;	--   and size.

CONSTANT RX8PHDRMEM      = H"70000" ;	-- Pulse header table base
CONSTANT RX8PHDRSIZE     = H"04000" ;	--   address and size.


-- ************************************
-- *                                  *
-- * RVP8/Rx Filter FPGA Memory Block *
-- *                                  *
-- ************************************

CONSTANT RX8FILTERSZ     = H"80000" ;	-- Memory size (512K DWORDs)
CONSTANT RX8FILTERHIB = LOG2(RX8FILTERSZ) - 1 ;

CONSTANT RX8LINKMEM      = H"00100" ;	-- IFD uplink transmitter memory
CONSTANT RX8LINKSIZE     = H"00020" ;	--   and size.

CONSTANT RX8RNGMEM       = H"04000" ;	-- Range mask data pattern memory
CONSTANT RX8RNGSIZE      = H"04000" ;	--   and size.

					-- Hole: ( 0x08000 - 0x0FFFF )

CONSTANT RX8DIFMEM       = H"10000" ;	-- Direct IF data sample memory
CONSTANT RX8DIFSIZE      = H"10000" ;	--   and size.
  CONSTANT RX8DIFMAGIC     = H"03BF" ;	-- Magic number at start of each pulse
					--   (upper RX8BANKBITS bits are BANK #)

CONSTANT RX8TGDMEM       = H"40000" ;	-- Trigger generator memory
CONSTANT RX8TGDSIZE      = H"40000" ;	--   and size.

  -- Opcodes in pulse descriptor words.  These are located in low
  -- memory for the start of each sequence, as well as within the
  -- sequences themselves for each new pulse.
  --
  CONSTANT RX8TGADRHIB     = 16 ;	-- High bit of address field
  CONSTANT RX8TGWAVEINC    = 17 ;	-- "Increment waveform" opcode bit
  CONSTANT RX8TGINTABLE    = 18 ;	-- "Interruptible" opcode bit
  CONSTANT RX8TGPHASELO    = 24 ;	-- Low and high bits of Tx phase
  CONSTANT RX8TGPHASEHI    = 31 ;

  -- Opcodes in pattern control words within each pulse
  --
  CONSTANT RX8TGCNTHIB     = 15 ;	-- High bit of iteration count field
  CONSTANT RX8TGDATA       = 16 ;	-- "Data" vs "Hold" opcode bit
  CONSTANT RX8TGCONT       = 17 ;	-- "Continue" opcode bit

  CONSTANT RX8BANKBITS     =  6 ;	-- Number of bits in trigger bank

-- ************************************
-- *                                  *
-- * Global Circuit Board Definitions *
-- *                                  *
-- ************************************

-- ------------------------------
-- Interrupt UNIT assignments to ISR register
--
CONSTANT RX8INTUNIT_DMA      =  0 ;	-- DMA interrupts
CONSTANT RX8INTUNIT_IQLOG    =  1 ;	-- IQ Logger
CONSTANT RX8INTUNIT_DIRIF    =  2 ;	-- Direct IF logger
CONSTANT RX8INTUNIT_TIMER0   =  3 ;	-- Counter/Timer #0
CONSTANT RX8INTUNIT_TIMER1   =  4 ;	-- Counter/Timer #1
CONSTANT RX8INTUNIT_TIMER2   =  5 ;	-- Counter/Timer #2

-- ------------------------------
-- There are 120 shared signal lines between the two PLDs.  These are
-- used to help distribute and share the overall board functions.
-- Unfortunately, AHDL has very little support for split designs; so
-- make sure that the In/Out definitions match between the two chips.
--
CONSTANT IOC_TGBLANKED     = 103 ;	-- Triggers are blanked now
CONSTANT IOC_NEWBANKBEGUN  = 102 ;	-- A new Trigger bank has freshly begun

CONSTANT IOC_DNLINKIN      = 101 ;	-- The softplane serial uplink and
CONSTANT IOC_DNLINKOUT     = 100 ;	--   downlink are routed through to
CONSTANT IOC_UPLINKIN      =  99 ;	--   the SPLCOMMON core on the other
CONSTANT IOC_UPLINKOUT     =  98 ;	--   chip.

CONSTANT IOC_PIPEGAP       =  97 ;	-- Pipelined pulse gap
CONSTANT IOC_IQAVAIL       =  96 ;	-- (I,Q) word is available

CONSTANT IOC_INT_TIMER2    =  95 ;	-- Counter/Timer #2 interrupt
CONSTANT IOC_INT_TIMER1    =  94 ;	-- Counter/Timer #1 interrupt
CONSTANT IOC_INT_TIMER0    =  93 ;	-- Counter/Timer #0 interrupt
CONSTANT IOC_INT_DIRIF     =  92 ;	-- Direct IF logger interrupt

CONSTANT IOC_CURWAVE       =  91 ;	-- Current waveform NZ if set

CONSTANT IOC_REFCLK        =  90 ;	-- Reference clock from filter chip

CONSTANT IOC_DAC_SCLK      =  89 ;	-- Clock, chip select and data input
CONSTANT IOC_DAC_CS        =  88 ;	--   lines for the 14-bit serially
CONSTANT IOC_DAC_DIN       =  87 ;	--   loaded DAC (LOG output).

CONSTANT IOC_CURBANKHI     =  86 ;	-- Six bits of current trigger bank
CONSTANT IOC_CURBANKLO     =  84 ;	--   MUX'ed onto three lines

CONSTANT IOC_TPB           =  83 ;	-- Test point B \    Physically 
CONSTANT IOC_TPA           =  82 ;	-- Test point A / constrained here

CONSTANT IOC_IQDATAHI      =  81 ;	-- 32-bit (I,Q) packed data MUX'ed
CONSTANT IOC_IQDATALO      =  66 ;	--   onto sixteen I/O lines.

CONSTANT IOC_IFDATAHI      =  65 ;	-- 16-bit IF receive data MUX'ed onto
CONSTANT IOC_IFDATALO      =  58 ;	--  eight I/O lines (to save lines)

CONSTANT IOC_IFDSIGDET     =  57 ;	-- Fiber signal is detected
CONSTANT IOC_IFDUPLINK     =  56 ;	-- Uplink to IFD

CONSTANT IOC_TGUSERHI      =  55 ;	-- Low 18 triggers multiplexed onto
CONSTANT IOC_TGUSERLO      =  47 ;	--  nine I/O lines (to save lines)

CONSTANT IOC_SECSYNC       =  46 ;	-- Sync pretrigger to secondary Rx
CONSTANT IOC_TRIGIN        =  45 ;	-- External trigger input

CONSTANT IOC_AQCLK1X       =  44 ;	-- 1x Aq Clock from master FPGA
CONSTANT IOC_RESET_        =  43 ;	-- System reset (active low)

CONSTANT IOC_MPM_RDACK     =  42 ;	-- MPM Read acknowledge
CONSTANT IOC_MPM_RDREQ     =  41 ;	-- MPM Read request
CONSTANT IOC_MPM_WRACK     =  40 ;	-- MPM Write acknowledge
CONSTANT IOC_MPM_WRREQ     =  39 ;	-- MPM Write request
CONSTANT IOC_MPM_DLAT      =  38 ;	-- MPM Latch write data
CONSTANT IOC_MPM_ALAT      =  37 ;	-- MPM Latch write address

CONSTANT IOC_SMADRS        =  36 ;	-- PCI address state
CONSTANT IOC_CSRRD         =  35 ;	-- CSR read cycle
CONSTANT IOC_CSRWR         =  34 ;	-- CSR write cycle
CONSTANT IOC_MASGETD       =  33 ;	-- Master gets data from Filter
CONSTANT IOC_PCIHI         =  32 ;	-- \  Shared PCI
CONSTANT IOC_PCILO         =   1 ;	-- /   Data Bus

-- There are four fast I/O pins that are driven by the master FPGA
-- and received by both.  These are intended for common clocks.
--
CONSTANT FIO_PCIDLYCLK =   2 ;		-- PCI clock (plus delay)
CONSTANT FIO_AQCLK2X   =   1 ;		-- 2x Acquisition clock

-- Other hardware constants.  The serial BOOT data is set to transition
-- in the middle of the reference clock because the Master FPGA chip
-- does not get that clock directly.  The midpoint transitions allow
-- some clock skew, but also sets an upper bound on the clock frequency
-- of, perhaps 20MHz.
--
CONSTANT RX8CLKFREQ    = 10000000 ;	-- Reference clock frequency
CONSTANT RX8BOOTMIDCLK = 1 ;		-- Boot data transitions in middle
