/* **********************************************************************
 * *                                                                    *
 * *     Hardware Register Mappings for the RVP8/Tx Receiver Board      *
 * *                                                                    *
 * **********************************************************************
 * File: rda/pcicards/rvp8tx.inc
 *
 *                        COPYRIGHT (c) 2001  BY
 *          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
 * 
 * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
 * ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
 * INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
 * COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
 * OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
 * TRANSFERED.
 *
 *
 * = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 * This file must be manually maintained in parallel with its C
 *   companion file: rvp8tx.h.  The syntax between C and AHDL
 *        is too different to try to patch automatically.
 * = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 */
#ifndef SIGMET_RVP8TX_H
#define SIGMET_RVP8TX_H 1

/* **************************************
 * *                                    *
 * * RVP8/Tx Control/Status Definitions *
 * *                                    *
 * **************************************
 */
#define TX8CSRSZ           64	/* CSR decoded address space (DWORDs) */

/* TxDAC waveform control registers
 */
struct rvp8txWaveDAC {
  /* TxDAC Control/Status register for each AD9772A chip.  Many of the
   * pins on the chip are directly written/read from here.
   */
  UINT4 iCSR ;
#define TX8DAC_MOD0         0 	/* Chip MOD0 line */
#define TX8DAC_MOD1         1 	/* Chip MOD1 line */
#define TX8DAC_DIV0         2 	/* Chip DIV0 line */
#define TX8DAC_DIV1         3 	/* Chip DIV1 line */
#define TX8DAC_PLLOCK       4 	/* Chip PLLOCK line (RD-Only) */
#define TX8DAC_PLLVDD       5 	/* Chip PLLVDD line (RD-Only) */
#define TX8DAC_NCOENAB      8 	/* Enable NCO functions */
#define TX8DAC_PULSED       9 	/* Pulsed sinewave output (vs CW) */
#define TX8DAC_PHASEMOD    10 	/* Apply phase modulation to each pulse */
#define TX8DAC_ABRUPTPH    11	/* Make abrupt phase changes */

#define TX8DAC_CHIPBITS \
  ( BIT(TX8DAC_MOD0) | BIT(TX8DAC_MOD1) | BIT(TX8DAC_DIV0) | BIT(TX8DAC_DIV1) )

  /* TxDAC Numerically Controlled Oscillator (NCO) phase increment
   * register sets the output frequency as a binary angle increment.
   * The FMOD register contains fractional p/q frequency control
   * values that let us generate most frequencies precisely, not just
   * approximately.  These registers are ReadOnly to save internal
   * logic.
   */
  UINT4 iFreq ;			/* Phase increment per cycle */
  UINT4 iFMod ;			/* Modulo frequency counters */
#define NCOPHASEBITS  22	/* Number of bits in NCO phase counter */
#define FREQMODBITS   10	/* Fractional p/q frequency adjustment */

  /* The CW register holds fixed phase and amplitude offsets that are
   * used when waveform generation is OFF.  This register is ReadOnly
   * to save internal logic.
   */
  UINT4 iCWPhzAmp ;		/* Phase in upper bits, Amplitude in lower */
#define CWPHASEBITS    8	/* Number of bits of phase adjustment [0-360) */
#define CWAMPLBITS    10	/* Number of bits of amplitude scaling [0-1) */

  UINT4 pad4x4[4] ;
} ;

/* Overall PCI Control/Status structure
 */
struct rvp8tx_csr {
  UINT4 iReset ;		/* Write RDA_RESET_DATA ==> reset */
  UINT4 iISR ;			/* Interrupt Service Register */

  UINT4 pad02x01[0x01] ;

  /* ------------------------------
   * Board Edge LEDs.  Note that the "Always ON" code is assigned
   * the value zero so that all of the LEDs light up upon reset.
   */
  UINT4 iRedLED ;		/* Red LED options */
#define TX8REDLED_ON        0	/*   On always */
#define TX8REDLED_OFF       1	/*   Off always */
#define TX8REDLED_PCIACT    2	/*   Shows PCI access */

  UINT4 iGrnLED ;		/* Green LED options */
#define TX8GRNLED_ON        0	/*   On always */
#define TX8GRNLED_OFF       1	/*   Off always */

  UINT4 iVisLED ;		/* Green faceplate LED options */
#define TX8VISLED_ON        0	/*   On always */
#define TX8VISLED_OFF       1	/*   Off always */

  /* ------------------------------
   * PCI Read/Write 32-bit diagnostic mirror
   */
  UINT4 iPCIMirror ;		/* Reads back what's written */

  UINT4 pad07x01[ 0x01 ] ;
   /* ------------------------------
   * General purpose Counter/Timers
   */
#define TX8NTIMERS          3	 /* Number of timers onboard */
  UINT4 iTimerCSRs[TX8NTIMERS] ; /* Control/Status for each timer */
#define TX8TIMER0_NBITS    20	 /* Number of bits in each counter/timer */
#define TX8TIMER1_NBITS    16
#define TX8TIMER2_NBITS    16

  /* ------------------------------
   * Digital POT reference voltages for each Tx section
   */
  UINT4 iPot ;			/* Control register (no readback) */
#define TX8POT_CLKA         0 	/*    Clock "A" channel */
#define TX8POT_UPA          1 	/*    Count Up "A" channel */
#define TX8POT_CLKB         2 	/*    Likewise for "B" */
#define TX8POT_UPB          3

#define TX8POT_SPAN       128	/* Overall span of the digial POT */

  /* ------------------------------
   * BNC (External Clock) line configuration
   */
  UINT4 iBNC ;			/* Control/Status register */
#define TX8BNC_OUTDIV0      0	/*   Output clock divisor */
#define TX8BNC_OUTDIV1      1
#define TX8BNC_OUTDIV2      2
#define TX8BNC_OUTDIV3      3
#define TX8BNC_OUTDIV4      4
#define TX8BNC_MODE0        8	/*   Mode of operation (See definitions */
#define TX8BNC_MODE1        9	/*     in pcicards_lib.h) */
#define TX8BNC_MODE2       10

  /* ------------------------------
   * Master Tx Sampling Clock/VCXO for Rev.A/B/C boards
   */
  UINT4 iTxClkA ;		/* Control/Status register */
#define TX8CLKA_DENOMLO     0	/*   Denominator (minus one) */
#define TX8CLKA_DENOMHI     8
#define TX8CLKA_NUMERLO    12	/*   Numerator (minus one) */
#define TX8CLKA_NUMERHI    20
#define TX8CLKA_PLLSRC0    24	/*   Which clock to lock to */
#define TX8CLKA_PLLSRC1    25
#define TX8CLKA_PLLENAB    26	/*   Enable PLL feedback */
#define TX8CLKA_PLLERROR   27	/*   Locking error (sticky) since last RD */

#ifdef SIGMET_PCICARDS_LIB_H
#if (TX8MAXNUMDEN != 2<<(TX8CLKA_DENOMHI - TX8CLKA_DENOMLO)) || \
    (TX8MAXNUMDEN != 2<<(TX8CLKA_NUMERHI - TX8CLKA_NUMERLO))
#error Please manually maintain TX8MAXNUMDEN
#endif
#endif

  /* ------------------------------
   * Master Tx Sampling Clock/VCXO for Rev.D boards
   */
  UINT4 iTxClkD ;		/* Control/Status register */
#define TX8CLKD_PLL_LE      0	/*   Direct control of the LE, DATA, */
#define TX8CLKD_PLL_DATA    1	/*     and CLK serial inputs of the */
#define TX8CLKD_PLL_CLK     2	/*     LMX2306 PLL chip. */
#define TX8CLKD_PLLSRC0     4	/*   Which clock to lock to */
#define TX8CLKD_PLLSRC1     5
#define TX8CLKD_PLLERROR    8 	/*   Lock error (from chip LD pin) */

  /* ------------------------------
   * Softplane common control/status register.  Bit definitions can be
   * found in pcicards_lib.h.
   */
  UINT4 iSPLCom ;

  /* ------------------------------
   * Control/Status structures for each TxDAC output channel.
   */
  struct rvp8txWaveDAC txChan[2] ;

  /* ------------------------------
   * TxDAC common control elements, and control structures for each
   * individual waveform output channel.
   */
  UINT4 iDACCom ;		/* Control/Status register */
#define TX8DACOM_SYNCNCO    0 	/*   Sync both chan's NCOs (WR-Only) */

  UINT4 pad21x1F[ 0x1F ] ;
} ;

/* **********************************
 * *                                *
 * * RVP8/Tx On-Board Shared Memory *
 * *                                *
 * **********************************
 */
#define TX8MEMSZ       0x80000	/* Total memory size (512K DWORDs) */

#define TX8WAVESIZE ( TX8MEMSZ / 2 )
struct rvp8txChanMem {		/* Single channel memory definitions */
  UINT4 iWaveTab[ TX8WAVESIZE ] ;
} ;
struct rvp8tx_mem {		/* Overall memory definition */
  struct rvp8txChanMem Ch[2] ;	/* Merely two copies of each channel */
} ;

/* ************************************
 * *                                  *
 * * Global Circuit Board Definitions *
 * *                                  *
 * ************************************
 */

/* ------------------------------
 * Interrupt UNIT assignments to IOR Mail Box register
 */
#define TX8INTUNIT_TIMER0     0 /* Counter/Timer #0 */
#define TX8INTUNIT_TIMER1     1 /* Counter/Timer #1 */
#define TX8INTUNIT_TIMER2     2 /* Counter/Timer #2 */

#endif /* #ifndef SIGMET_RVP8TX_H */
