/* **********************************************************************
 * *                                                                    *
 * *       Hardware Register Mappings for the IO-62 PCI I/O Board       *
 * *                                                                    *
 * **********************************************************************
 * File: rda/pcicards/io62.h
 *
 *                        COPYRIGHT (c) 2002  BY
 *          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
 * 
 * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
 * ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
 * INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
 * COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
 * OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
 * TRANSFERED.
 */
#ifndef SIGMET_IO62_H
#define SIGMET_IO62_H 1

/* = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 * This file must be manually maintained in parallel with its PLD
 *   companion file: io62.inc.  The syntax between C and AHDL
 *        is too different to try to patch automatically.
 * = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 */

/* **************************************
 * *                                    *
 * * RVP8/Rx Control/Status Definitions *
 * *                                    *
 * **************************************
 */
#define IO62CSRSZ         128	/* CSR decoded address space (DWORDs) */
struct io62_csr {		
  UINT4 iReset ;		/* Write RDA_RESET_DATA ==> reset */
  UINT4 iISR ;			/* Interrupt Service Register */

  UINT4 pad02x01[0x01] ;

  /* ------------------------------
   * Board Edge LEDs.  Note that the "Always ON" code is assigned
   * the value zero so that all of the LEDs light up upon reset.
   */
  UINT4 iRedLED ;		/* Red LED options */
#define IO62REDLED_ON        0	/*   On always */
#define IO62REDLED_OFF       1	/*   Off always */
#define IO62REDLED_PCIACT    2	/*   Shows PCI access */

  UINT4 iGrnLED ;		/* Green LED options */
#define IO62GRNLED_ON        0	/*   On always */
#define IO62GRNLED_OFF       1	/*   Off always */

  UINT4 iVisLED ;		/* Green faceplate LED options */
#define IO62VISLED_ON        0	/*   On always */
#define IO62VISLED_OFF       1	/*   Off always */

  /* ------------------------------
   * Front Panel Display Control
   */
  UINT4 iFpdCSR ;		/* Control/Status */
  UINT4 iFpdData ;		/* Direct character read/write */

  /* ------------------------------
   * Dual 14-bit DAC Outputs
   */
  UINT4 iDACs[2] ;

  /* ------------------------------
   * Two on-board relays; Relay control in bits <1:0>
   */
  UINT4 iRelayCSR ;

  /* ------------------------------
   * Miscellaneous monitor/force bits.  These signals will generally
   * be driven by logic that is internal to the FPGA.  However, we can
   * force the lines Hi/Lo under program control, and can also
   * readback the present state of the outputs.
   */
  UINT4 iMonForce ;		/* Monitor/Force Bits */
#define IO62MF_TRIG0H        0	/*   Force trigger drivers high */
#define IO62MF_TRIG1H        1
#define IO62MF_TRIG2H        2
#define IO62MF_TRIG3H        3
#define IO62MF_TRIG0L        4	/*   Force trigger drivers low */
#define IO62MF_TRIG1L        5
#define IO62MF_TRIG2L        6
#define IO62MF_TRIG3L        7
#define IO62MF_TRIG0         8	/*   Current state of trigger drivers */
#define IO62MF_TRIG1         9
#define IO62MF_TRIG2        10
#define IO62MF_TRIG3        11
#define IO62MF_TTY0XH       12	/*   Force TTY transmitters high */
#define IO62MF_TTY1XH       13
#define IO62MF_TTY0XL       14	/*   Force TTY transmitters low */
#define IO62MF_TTY1XL       15
#define IO62MF_TTY0X        16	/*   Current state of TTY transmitters */
#define IO62MF_TTY1X        17
#define IO62MF_TTY0R        18	/*   Current state of TTY receivers */
#define IO62MF_TTY1R        19

  /* ------------------------------
   * General purpose Counter/Timers
   */
#define IO62NTIMERS          3	  /* Number of timers onboard */
  UINT4 iTimerCSRs[IO62NTIMERS] ; /* Control/Status for each timer */
#define IO62TIMER0_NBITS    20	  /* Number of bits in each counter/timer */
#define IO62TIMER1_NBITS    16
#define IO62TIMER2_NBITS    16

  /* ------------------------------
   * Selection of shared I/O status lines which are copied to other
   * boards via the softplane, and which can serve as counter/timer
   * inputs.
   */
  UINT4 iShareCSR ;		/* Shared line input sources */
#define IO62SHARE_LINE0      0	/*   Readback of status input lines */
#define IO62SHARE_LINE1      1
#define IO62SHARE_LINE2      2
#define IO62SHARE_MODEL0     8	/*   Which line hookup model is */
#define IO62SHARE_MODEL1     9	/*     being used. */

  /* ------------------------------
   * General purpose I/O lines, allocated in groups of eight.  The
   * five (RD-Only) GIO CSRs assign the configuration of each block of
   * signals, organized as four signal pairs.
   */
#define IO62GIO_NPAIRS      20	/* Number of I/O line-pairs */

  UINT4 gioCSRs[ IO62GIO_NPAIRS / 4 ] ;
#define IO62GIO_RSDRIVE0     0	/*  Independent enable lines for the */
#define IO62GIO_RSDRIVE1     1	/*    four RS422 drivers.  Only used */
#define IO62GIO_RSDRIVE2     2	/*    in RS422 and RSTTLPULL modes. */
#define IO62GIO_RSDRIVE3     3

#define IO62GIO_RSCHIPS0     4	/*  Selects whether each signal pair */
#define IO62GIO_RSCHIPS1     5	/*    is driven/received as RS422 */
#define IO62GIO_RSCHIPS2     6	/*    or as TTL.  Only used in RS422 */
#define IO62GIO_RSCHIPS3     7	/*    and RSTTLPULL modes. */

#define IO62GIO_INTERNAL0    8	/*  Selects whether each signal pair */
#define IO62GIO_INTERNAL1    9	/*    is driven/received by internal */
#define IO62GIO_INTERNAL2   10	/*    logic or via the PCI registers. */
#define IO62GIO_INTERNAL3   11

#define IO62GIO_DCONFIG0    12	/*  Overall digital I/O configuration */
#define IO62GIO_DCONFIG1    13
  #define IO62DCF_DISABLED    0 /*    All functions disabled */
  #define IO62DCF_TTLDRIVE    1 /*    Configure as eight TTL drivers */
  #define IO62DCF_RS422       2 /*    Configure as four RS422 Tx/Rx */
  #define IO62DCF_RSTTLPULL   3 /*    As above, but w/ TTL-In & Pulls */

#define IO62GIO_RSTERMS     14	/*  Pairwise RS422 terminators */
#define IO62GIO_PULLUP      15	/*  +5V pullup, else GND pulldown */

  UINT4 pad15x01[0x01] ;

  /* Read/Write data levels (20-bit) for the "+" and "-" signal pins,
   * and ReadOnly bits being received by the unused TTL or RS232
   * receiver.
   */
  UINT4 gioData[2] ;
  UINT4 gioDAlt[2] ;

  /* ------------------------------
   * PCI Read/Write 32-bit diagnostic mirror
   */
  UINT4 iPCIMirror ;		/* Reads back what's written */

  /* ------------------------------
   * Onboard trigger driver control register
   */
  UINT4 iTrigs ;		/* Trigger source selection */
#define IO62TRIGS_DRIVEN0    0	/*   Line driver #0 hooked to a trigger */
#define IO62TRIGS_DRIVEN1    1	/*               #1 */
#define IO62TRIGS_DRIVEN2    2	/*               #2 */
#define IO62TRIGS_DRIVEN3    3	/*               #3 */

#define IO62TRIGS_D0TG0TG4   4	/*   Use Trig0/Trig4 for line #0 */
#define IO62TRIGS_D1TG1TG5   5	/*   Use Trig1/Trig5 for line #1 */
#define IO62TRIGS_D2TG2PL0   6	/*   Use Trig2/Pol0  for line #2 */
#define IO62TRIGS_D3TG3PL1   7	/*   Use Trig3/Pol1  for line #3 */

#define IO62TRIGS_PHASEOUT   8 	/*   Drive 8-bit phase on I/O lines #4-11 */
#define IO62TRIGS_PHASESET   9	/*   Use fixed phase, not live softplane */

#define IO62TRIGS_PHASELO   24	/*   Fixed phase that will be used when */
#define IO62TRIGS_PHASEHI   31	/*     PHASESET bit is set. */

  /* ------------------------------
   * A/D converter control and data
   */
  UINT4 iADCSR ;		/* A/D converter control/status register */
#define IO62ADCSR_SAMPLO     0	/*   Present 12-bit A/D sample */
#define IO62ADCSR_SAMPHI    11	/*     low and high bits */
#define IO62ADCSR_OTR       12	/*   Out-of-range bit */
#define IO62ADCSR_MINIMIZE  13	/*   Replace instantaneous A/D samples */
#define IO62ADCSR_MAXIMIZE  14	/*     with Min/Max values. */
#define IO62ADCSR_AMUX0     16	/*   Manually selected analog MUX */
#define IO62ADCSR_AMUX1     17
#define IO62ADCSR_AMUX2     18
#define IO62ADCSR_AMUXPCI   19	/*   Force AMUX<2:0>, else internal */

#define NUMADCBITS (1 + IO62ADCSR_SAMPHI - IO62ADCSR_SAMPLO)

  /* ------------------------------
   * Board-to-Board serial protocol
   */
  UINT4 iB2B ;			/* Control/Status Register */
#define IO62B2B_BITLO       0 	/*   Data bits sent/received to/from */
#define IO62B2B_BITHI       7 	/*     the other IO62 card. */
#define IO62B2B_TXCYCLE    28 	/*   These bits toggle on each packet */
#define IO62B2B_RXCYCLE    29 	/*     that is sent/received. */
#define IO62B2B_ENA_PHYS   31 	/*   Enable IO62 card's physical I/O */

  /* Note: IO62B2B_NBITS definition resides in pcicards_lib.h */

  /* ------------------------------
   * Softplane common control/status register.  Bit definitions can be
   * found in pcicards_lib.h.
   */
  UINT4 iSPLCom ;

  UINT4 pad1Fx01[0x01] ;

  /* ------------------------------
   * Standard Remote Backpanel Access Registers
   */
  UINT4 iCPCnt ;		/* Connector panel control register */
#define IO62CPCNT_ENA_PHYS   0	/*   Enable IO62 card's physical I/O */
#define IO62CPCNT_ENA_PANL   1	/*   Enable backpanel's physical I/O */
#define IO62CPCNT_ENA_CTRL   2	/*   Enable serial control stream */
#define IO62CPCNT_ENA_BOOT   3 	/*   Enable boot chip functions */
#define IO62CPCNT_ENA_MAIN   4 	/*   Enable main chip functions */
#define IO62CPCNT_RELAY0     5 	/*   Three onboard relays */
#define IO62CPCNT_RELAY1     6 
#define IO62CPCNT_RELAY2     7 
#define IO62CPCNT_RCOIL0     8 	/*   Four external relay coils */
#define IO62CPCNT_RCOIL1     9 
#define IO62CPCNT_RCOIL2    10 
#define IO62CPCNT_RCOIL3    11 
#define IO62CPCNT_TMON0H    12 	/*   Force Monitor BNCs high */
#define IO62CPCNT_TMON1H    13 
#define IO62CPCNT_TMON0L    14 	/*   Force Monitor BNCs low */
#define IO62CPCNT_TMON1L    15 
#define IO62CPCNT_AMUX0     16 	/*   Manually selected analog MUX */
#define IO62CPCNT_AMUX1     17 
#define IO62CPCNT_AMUX2     18 
#define IO62CPCNT_AMUX3     19 
#define IO62CPCNT_AMUX4     20 
#define IO62CPCNT_AMUXPCI   21 	/*   Force AMUX<4:0>, else internal */
#define IO62CPCNT_LEDOFF    22 	/*   Force LED Off */
#define IO62CPCNT_DGDRIVE0  23	/*   Two spare DG RS-422 pins on J3 */
#define IO62CPCNT_DGDRIVE1  24	/*     are drivers; else receivers. */
#define IO62CPCNT_DGDATA0   25	/*   Data being output by DG pins, */
#define IO62CPCNT_DGDATA1   26	/*     if configured as outputs. */

  UINT4 iCPSts ;		/* Connector panel status register (Read-Only) */
#define IO62CPSTS_CODE_LOB   0 	/*   High/Low bits of main code rev */
#define IO62CPSTS_CODE_HIB   5 	/*     (6 bits) */
#define IO62CPSTS_JTAGBUSY   6 	/*   Busy with JTAG now */
#define IO62CPSTS_SERCYCLE   7	/*   Toggles each serial uplnk cycle */
#define IO62CPSTS_DGDATA0    8	/*   Data seen on DG pins, read back */
#define IO62CPSTS_DGDATA1    9	/*     from actual panel lines. */

  UINT4 iCPSerialNum ;		/* Serial number of the backpanel */
  UINT4 iCPBoardRev ;		/* Board revision number */
  UINT4 iCPPatchLev ;		/* Board patch level (1=Orig, etc) */

  UINT4 iCPGio[ 5 ] ;		/* General purpose digital I/O */
#define IO62CPGIO_USERLO     0  /*   Low bit of user data word */
#define IO62CPGIO_USERHI    19 	/*   High bit of user data word */
#define IO62CPGIO_DRIVERS   20 	/*   Output drivers (vs input receivers) */

  /* ------------------------------
   * ORDA (RVP8 side) remote backpanel access registers
   */
  UINT4 iORDACnt ;		/* Control Register */
#define ORDACNT_ENA_PHYS     0	/*   Enable IO62 card's physical I/O */
#define ORDACNT_PRATE0       1	/*   Pulse rate interval bits */
#define ORDACNT_PRATE1       2
#define ORDACNT_PRATE2       3
#define ORDACNT_LEDOKAY      4	/*   Turn on the RVP8 'okay' LED */
#define ORDACNT_AMUX0        5 	/*   Analog MUX select */
#define ORDACNT_AMUX1        6
#define ORDACNT_SPARE1       7	/*   Spare output driver */
#define ORDACNT_RADSTS0      8	/*   Radiate/Test status */
#define ORDACNT_RADSTS1      9
#define ORDACNT_RADSTS2     10
#define ORDACNT_RXPROTOK    11	/*   Rx protection handshake is okay */
#define ORDACNT_TP_A_0      24	/*   Test point 'A' 4-bit select code */
#define ORDACNT_TP_A_3      27
#define ORDACNT_TP_B_0      28	/*   Test point 'B' 4-bit select code */
#define ORDACNT_TP_B_3      31

  /* Note: ORDA testpoint and radiate status definitions reside in
   * pcicards_lib.h
   */

  /* ------------------------------
   * MIT/LL TDWR V1 support for standard remote panel
   */
  UINT4 iTdwrV1CSR ;		/* Control/Status Register */
#define TDWRV1_ENA_PHYS      0	/*   Enable IO62 card's physical I/O */
#define TDWRV1_MODE0         4	/* Mode of operation */
#define TDWRV1_MODE1         5

#define TDWRV1_SAMP5UP       8	/* Synchronously sampled I/O status lines */
#define TDWRV1_SAMP5DN       9	/*   during rising/falling edges of user */
#define TDWRV1_SAMP6UP      10	/*   triggers. */
#define TDWRV1_SAMP6DN      11
#define TDWRV1_SAMP7UP      12

  /* ------------------------------
   * Serializer supporting arbitrary line protocols
   */
  UINT4 iSerialCSR0 ;		/* Control/Status */
  UINT4 iSerialData0 ;		/* Serialized Rx/Tx data */

  UINT4 pad2Ex02[0x02] ;

  /* ------------------------------
   * Optional Shaft encoder inputs
   */
  UINT4 iShaftAZ ;		/* Status registers for Azimuth and */
  UINT4 iShaftEL ;		/*   Elevation encoders (Read Only) */

  /* The number of bits in the up/dn counter is based on a maximum count
   * rate of 2000 quadrature increments/second, and a maximum time between
   * sampling of 15ms.
   */
  #define IO62SHAFTNUMBITS   6	/* Size of up/dn counter */

  #define IO62SHAFTINDEX    12	/* Index pulse current level */
  #define IO62SHAFTINDEXTOG 13	/* Index pulse has toggled  \ Cleared on */
  #define IO62SHAFTERROR    14	/* A/B Protocol error       /  PCI read */

  UINT4 pad32x2E[0x2E] ;

  /* ------------------------------
   * A/D logger RAM is mapped into the upper portion of the CSR space.
   * The upper ten bits of these words have the accumulation count,
   * and the lower 22 bits hold the accumulated A/D values.
   */
#define ADCLOGRAMSIZE  32
  UINT4 iADClogRAM[ ADCLOGRAMSIZE ] ;

#define ADCDIFFCOUNT( SAMP, PREV ) ( ( ((SAMP)>>22) - ((PREV)>>22) ) & 0x000003FF )
#define ADCDIFFVALUE( SAMP, PREV ) ( (  (SAMP)      -  (PREV)      ) & 0x003FFFFF )
} ;

/* ************************************
 * *                                  *
 * * Global Circuit Board Definitions *
 * *                                  *
 * ************************************
 */

/* ------------------------------
 * Interrupt UNIT assignments to IOR Mail Box register
 */
#define IO62INTUNIT_TIMER0  0	/*  Counter/Timer #0 */
#define IO62INTUNIT_TIMER1  1	/*  Counter/Timer #1 */
#define IO62INTUNIT_TIMER2  2	/*  Counter/Timer #2 */
#define IO62INTUNIT_IOSER0  3	/*  I/O Serializer #0 */

#endif /* #ifndef SIGMET_IO62_H */
