/* ********************************
 * *                              *
 * *   Port I/O Definitions for   *
 * * Radar Interface Module (RIM) *
 * *        (rimiodef.h)          *
 * *                              *
 * ********************************
 */
#ifndef RIMIODEF_H
#define RIMIODEF_H

/* This file must be manually maintained in parallel with its PLD
 * companion file: rimiodef.inc.  The syntax between C and AHDL is
 * too different to try to patch automatically.
 */

/* The addressable port I/O space consists of 64 successive 8-bit
 * locations, beginning at the RIMIO_BASE base address.  The data bit
 * assignments are given below for each of the defined port addresses.
 *
 * Generally, each port supports both read and write access via the
 * INP and OUTP opcodes.  This allows you to read the present contents
 * of a location so that individual bits can be modified.
 *
 * Note that single-process access to the ports is generally assumed,
 * i.e., the operation of many ports assumes the consistency of
 * internal state between operations.  For example, the PLD external
 * memory is accessed by first setting up the RAM address, followed by
 * the actual read/write operations.  Clearly, this will not work
 * properly if the address is clobbered midway by another process.
 *
 * There is a naming convention for these macros.  Port I/O
 * subaddresses have names of the form "RIMIO_xxxx", while the bits
 * pertaining to that port are named "xxxx_yyyy".  This reduces the
 * likelyhood of using the wrong bit definitions with a given port
 * address, because the "xxxx" part of the names need to match.
 */

/* The I/O base address is kept within the basic 10-bit addressing
 * range of the PC.  This is because there is slightly better support
 * in LINUX for addressing I/O devices in this area.
 */
#define RIMIO_BASE            0x0140	/* Base port I/O address */
#define RIMIO_SPAN            0x0040	/*   and overall span */

/* An actual 16-bit port address, given the defined subaddress.
 */
#define RIMPORT(PNUM) ( RIMIO_BASE + ((PNUM) & (RIMIO_SPAN-1)) )

#define RIMIO_SERIAL_INCL          2	/* Serial number of this file */

/* ***********************
 * *                     *
 * * Fixed PLD Functions *
 * *                     *
 * ***********************
 */

/* The following functions are implemented primarily in the small
 * fixed PLD that can not be reprogrammed in the field.  As such,
 * these functions are kept to a minimum, and the assignments should
 * be viewed as more or less permanent.
 */

/* ------------------------------
 * Top-Level Control and Status
 *
 * The overall Control/Status register for the RIM ports is controlled
 * by the smaller PLD.  Its purpose is to disconnect the large PLDs
 * from the ISA bus during the times that their I/O signal pins are
 * undefined.  When TOPCSR_ALLOWIO is set, then ISA bus port I/O to
 * all addresses other than RIMIO_TOPCSR and RIMIO_JTAG will be passed
 * along to the large PLDs.
 *
 * The small PLD enforces a 15usec maximum duration on the ISA "wait"
 * signal.  This is to prevent the bus (and LINUX) from hanging as a
 * result of an error in new PLD code.  If the 15usec is exceeded, the
 * the cycle is terminated and the TOPCSR_TIMEOUT bit is set.  That
 * bit can be manually cleared by writing a zero to it.
 */
#define RIMIO_TOPCSR            0x00	/* Top-Level Control/Status */
#define TOPCSR_ALLOWIO             0	/*   Allow I/O to all PLDs.
					 *     (cleared on system reset) */
#define TOPCSR_TIMEOUT             1	/*   ISA wait terminated after 15usec */
#define TOPCSR_REV0                5	/*   Board revision level. */
#define TOPCSR_REV1                6	/*     These read-only bits tell the */
#define TOPCSR_REV2                7	/*     PC etch level (Rev.A,B,C, etc) */

/* ------------------------------
 * JTAG Control Lines.
 *
 * The two large PLDs are programmed in-circuit, and verified using a
 * common JTAG serial stream.  The JTAG lines are generated by the
 * smaller PLD that is programmed externally using a standard
 * programmer.  The ISP feature allows software upgrades of RIM code
 * to update the PLD contents as well.
 *
 * Note that the JTAG loadup is handled by the Altera JAM Player
 * utility, which is compiled separately and run during (or
 * immediately after) the boot sequence of the PC.
 */
#define RIMIO_PLDJTAG           0x01	/* JTAG Control Port */
#define PLDJTAG_TDO                0	/*   TDO (Read Only) */
#define PLDJTAG_TCK                1	/*   TCK (Write/Read) */
#define PLDJTAG_TMS                2	/*   TMS (Write/Read) */
#define PLDJTAG_TDI                3	/*   TDI (Write/Read) */

/* ------------------------------
 * Sofware Controlled ISA Reset
 *
 * Writing the magic number to this location is equivalent to the ISA
 * bus reset signal being asserted (at least, from the point of view
 * of the RIM PLDs).
 */
#define RIMIO_PCRESET           0x02	/* Simulate ISA bus reset */
#define PCRESET_MAGIC           0x3C	/*   magic number for reset */

/* ------------------------------
 * ASR9 Clock Control
 *
 * The three system clocks from the ASR9 (1.3, 2.6, and 10.3MHz) can
 * be replaced with locally generated clocks based on a 10MHz
 * oscillator.  This allows all of the RIM clock circuitry to
 * function, even when there is no external connection to the ASR9.
 *
 * The phase of the 10.3MHz clock can be adjusted so that its edges
 * align properly with the 2.6MHz clock.  This is to compensate for
 * unknown cable delays in the ASR9<->RIM ribbon cables.  There are
 * three delay selection bits, and a readback register that shows a
 * snapshot of the 10.3MHz clock in the vicinity of the rising edge of
 * the 2.6MHz clock, sampled at approximately 7ns intervals.
 *
 * The PC software should experiment with the delay settings until the
 * snapshot register shows the rising 10.3MHz clock transition
 * occuring close to time zero. Increasing the 3-bit delay shifts the
 * 10.3MHz clock "to the right", i.e., makes it later relative to the
 * 2.6Mhz rising edge.
 */
#define RIMIO_CLKCNT            0x03	/* Clock Control/Status */
#define CLKCNT_SIMULATE            0	/*   Simulate ASR9 system clocks */
#define CLKCNT_PHASE0              1	/*   1.3MHz simulated clock phase */
#define CLKCNT_PHASE1              2
#define CLKCNT_DELAY0              5	/*   Delay selection for 10.3MHz clock */
#define CLKCNT_DELAY1              6
#define CLKCNT_DELAY2              7

#define RIMIO_CLKSNAP           0x04	/* Clock sampling snapshot */
#define CLKSNAP_TP3                0	/*   Time +3 */
#define CLKSNAP_TP2                1	/*   Time +2 */
#define CLKSNAP_TP1                2	/*   Time +1 */
#define CLKSNAP_T00                3	/*   Time  0 */
#define CLKSNAP_TM1                4	/*   Time -1 */
#define CLKSNAP_TM2                5	/*   Time -2 */
#define CLKSNAP_TM3                6	/*   Time -3 */

/* The presence of all three ASR9 clocks is monitored by CLKSTS_NOCLK.
 * If this bit is set, but if CLKCNT_SIMULATE is clear, then internal
 * clocks will be forced with a delay code of zero.  This supplies
 * correctly timed fallback clocks in the event that the external
 * clocks fail during real operation.  Normal operation, using the old
 * delay value, will resume when the external clocks reappear.
 * However, when CLKCNT_SIMULATE is set, then the external clocks are
 * ignored, and the simulated clocks can be adjusted with the delay
 * selection.
 */
#define RIMIO_CLKSTS            0x05	/* Clock Status */
#define CLKSTS_NOCLK               0	/* No ASR9 clocks right now */
#define CLKSTS_NOCLK_STICKY        1	/* Clocks were gone in the past */
#define CLKSTS_013MHZ              5	/* Status of  1.3MHz input */
#define CLKSTS_026MHZ              6	/* Status of  2.6MHz input */
#define CLKSTS_103MHZ              7	/* Status of 10.3MHz input */

/* ------------------------------
 * Serial Number Management
 *
 * Each PLD reports its code version number, include file version
 * number, and licensing bits using a single multiplexed port.  Two of
 * the port data bits tell which value is being reported in the other
 * 6-bits.  These two select bits are read/write, and the report bits
 * are read-only.
 */
#define RIMIO_SERIAL_U1         0x08	/* Serial number data for U1 */
#define RIMIO_SERIAL_U2         0x09	/* Serial number data for U2 */
#define RIMIO_SERIAL_U3         0x0A	/* Serial number data for U3 */
#define SERIAL_REPORT0             0	/*   6-bit report field */
#define SERIAL_REPORT5             5
#define SERIAL_SELECT0             6	/*   2-bit select field */
#define SERIAL_SELECT1             7

#define SERIAL_SELECT_CODE         0	/* Selects PLD code version */
#define SERIAL_SELECT_INCL         1	/* Selects include file version */

/* **************************************
 * *                                    *
 * * Fully Field Programmable Functions *
 * *                                    *
 * **************************************
 */

/* The remainder of these I/O definitions are implemented in the field
 * programmable PLDs, and thus, can be changed if necessary.
 */

/* ------------------------------
 * Board Edge LEDs
 *
 * There are four user programmable LEDs mounted at the front
 * edge of the RIM board.  Each LED's state is controlled by
 * separate SET/CLR bits, rather than by a direct load.  This
 * allows the PC to set or change one LED without having to worry
 * about preserving the others.
 *
 * LEDs are allocated beginning with bit zero in each I/O byte.
 */
#define RIMIO_LED_SET           0x0C	/* LEDs to turn on  (write only) */
#define RIMIO_LED_CLR           0x0D	/* LEDs to turn off (write only) */
#define RIMIO_LED_STATE         0x0E	/* LED ON states    ( read only) */

/* ------------------------------
 * RAM Interface.
 *
 * The memory is organized as 4Mx8.  The address for reading and
 * writing can optionally autoincrement after each access.  This
 * allows blocks of memory to be accessed efficiently.  Also, for
 * example, choosing to increment after writes but not after reads
 * would permit efficient editing of a block of memory via
 * read-modify-write.
 *
 * To access the RAM, first setup the 22-bit starting address using
 * the RIMIO_MADRXX_XX ports.  Set the mode for address update using
 * RIMIO_MEMCTL, and then perform data reads and writes using
 * RIMIO_MEMDATA.
 */
#define RIMIO_MADR07_00         0x10	/* Low address bits */
#define RIMIO_MADR15_08         0x11	/* Middle address bits */
#define RIMIO_MADR21_16         0x12	/* (0, 0, High address bits) */

#define RIMIO_MEMCTL            0x13	/* Memory Access Control */
#define MEMCTL_RDINC               0	/*   Autoincrement after each read */
#define MEMCTL_WRINC               1	/*   Autoincrement after each write */

#define RIMIO_MEMDATA           0x14	/* RAM memory data itself */

/* ------------------------------
 * Synchronous/Asynchronous Serial Output.
 *
 * The RIM can generate a serial data stream having arbitrary
 * characteristics that are completely determined by the PC.  With
 * appropriate programming, this hardware interface will support any
 * type of serial output protocol.
 *
 * To accomplish this, the hardware interface merely outputs a
 * string of bits that are read from RAM; there is no particluar
 * interpretation ascribed to the sequence itself.  There are
 * eight such strings so that data buffering (no time gaps) can
 * be accomplished; and an optional idle pattern can be executed
 * whenever there is nothing else to do (See RAM Memory Map
 * below).
 *
 * The data and idle strings in RAM consist of a single data bit per
 * byte, plus a STOP bit indicating the end of the string.  The data
 * bit in the STOP location will also be transmitted, i.e., it is not
 * possible to have a zero-length bit pattern.  The advantage of using
 * a STOP bit in RAM (rather than data length counters in the PLD) is
 * that there is less internal state required in the PLD.
 *
 * The eight buffered data strings are output in an ascending
 * wraparound sequence using a 3-bit write pointer (WPTR) and 3-bit
 * read pointer (RPTR).  Whenever RPTR=WPTR, there is no more data to
 * output, and the IDLE string will be continually sent if the
 * SO_CSR_ENAIDLE bit is set.  To send a stream of data, first write
 * the data pattern plus stop bit to memory buffer number (WPTR+1)&7.
 * Then, write the NEWBUF bit, which will increment WPTR in a single
 * indivisible operation.  Continue writing new memory buffers and
 * setting NEWBUF, as long as (WPTR+1)&7 is not equal to RPTR.  The
 * later indicates that all buffers are presently in use.
 */

/* The buffer pointers and status of the transmitter are given in
 * RIMIO_SO_BUFSTS, which is entirely read-only.  WPTR is incremented
 * each time the SO_CSR_NEWBUF bit is written with a "1", and RPTR
 * will be incremented after each memory buffer is fully transmitted.
 * The SO_BUFSTS_XMTDATA and SO_BUFSTS_XMTIDLE bits indicate when each
 * type of data are being transmitted.  There are also two LEDs on the
 * front of the RIM board that can indicate this same state.
 */
#define RIMIO_SO_BUFSTS         0x16	/* Serial Read/Write Buffer Status */
#define SO_BUFSTS_RPTR0            0	/*   3-bit Read Pointer.  Indicates */
#define SO_BUFSTS_RPTR1            1	/*     the location of the next buffer */
#define SO_BUFSTS_RPTR2            2	/*     to be transmitted */
#define SO_BUFSTS_WPTR0            3	/*   3-bit Write Pointer.  Indicates */
#define SO_BUFSTS_WPTR1            4	/*     the location of the next buffer */
#define SO_BUFSTS_WPTR2            5	/*     to be filled in with data */
#define SO_BUFSTS_XMTDATA          6	/*   Data bits are being sent. */
#define SO_BUFSTS_XMTIDLE          7	/*   Idle bits are being sent. */

/* The SO_CSR_NEWBUF and SO_CSR_RESET bits are write-only; all others
 * are read/write.  Seting SO_CSR_RESET will bring about an immediate
 * and complete reset of all SIO functions, i.e., back to their
 * initial power-up condition: the SO_CSR_ENADATA and SO_CSR_ENAIDLE
 * bits are cleared, and RPTR and WPTR are both set to zero.
 */
#define RIMIO_SO_CSR            0x17	/* Serial Output Control/Status */
#define SO_CSR_NEWBUF              0	/*   SET each time a new buffer is ready */
#define SO_CSR_RESET               1	/*   Complete reset of SIO functions */
#define SO_CSR_ENADATA             2	/*   Data bit streams are enabled */
#define SO_CSR_ENAIDLE             3	/*   Idle bit stream is enabled */
#define SO_CSR_CLKPHZ0             4	/*   Bits adjust the output clock */
#define SO_CSR_CLKPHZ1             5	/*     phase within each bit time. */
#define SO_CSR_DFLTOUT             6	/*   Default output level */

/* The two LEDs that are normally associated with the serial
 * transmitter can also be reused as general-purpose indicators.
 */
#define RIMIO_SO_LEDS           0x18	/* Select LED functions */
#define SO_LEDS_DATA_CMD           0	/*   Data LED command (if not normal) */
#define SO_LEDS_IDLE_CMD           1	/*   Idle LED command (if not normal) */
#define SO_LEDS_DATA_NORM          2	/*   Data LED has normal function */
#define SO_LEDS_IDLE_NORM          3	/*   Idle LED has normal function */
#define SO_LEDS_DATA_STATE         4	/*   Data LED state */
#define SO_LEDS_IDLE_STATE         5	/*   Idle LED state */

/* Baud rate selection.  The serial output baud rate will be 153600
 * divided by one plus this value.
 */
#define RIMIO_SO_BAUD           0x19	/* Baud rate selection */

#define SO_MEMBIT_DATA             0	/* Memory bit: data */
#define SO_MEMBIT_STOP             1	/* Memory bit: end of string */
#define SO_MEMBIT_LEDON            2	/* Memory bit: turn on LED */

/* ------------------------------
 * RIM/ASR9/RVP7 Simulation Control
 *
 * Various input signals from the ASR9 can be simulated locally.  This
 * allows program development to proceed, even when there is no
 * external connection to the ASR9.  Subsystems can be simulated
 * individually, so that partial simulation can be used even with a
 * real connection to an ASR9.  For example, the ACP/ARP pulses can be
 * simulated in case the antenna is not actually rotating.
 *
 * The PRETO simulator is implemented as an array of desired time
 * intervals.  Likewise, the ASR9 and RVP7 (I,Q) simulators read
 * pulses of simulated data from RAM.  See the Memory Map definitions
 * below.
 * 
 * The ACP/ARP simulator produces ACP pulses at approximately 890Hz,
 * and an ARP pulse at every 4096th ACP.  The ARP therefore is
 * produced at approximatly 4.6 second intervals.
 */
#define RIMIO_SIMULATE          0x1B	/* ASR9 Simulation Control */
#define SIMULATE_PRETO             0	/*   Simulate PRETO */
#define SIMULATE_ACPARP            1	/*   Simulate ACP and ARP */
#define SIMULATE_ASR9IQ            2	/*   Simulate ALTC[11:0] */
#define SIMULATE_RVP7IQ            3	/*   Simulate RVP7 I/Q Data */

/* The simulated rate of ACP pulses is scaled by the following 8-bit
 * number as 1.3MHz / (1024 + 4*RIMIO_ACPSIM_RATE).  The rate is
 * preset to 109 on power up, giving a default ACP frequency of
 * 1.3MHz / (1024 + 4*109) = 890Hz.
 */
#define RIMIO_ACPSIM_RATE       0x1C	/* Simulated ACP rate */

/* ------------------------------
 * ASR9 Antenna Position
 *
 * The ASR9 generates 4096 Antenna Control Pulse (ACP) signals per
 * revolution, and one Antenna Reset Pulse (ARP) on each North mark
 * crossing.  Antenna azimuth position is maintained as a 12-bit count
 * of ACPs within each revolution, plus a 4-bit count of ARPs that
 * have been received so far.
 *
 * The antenna position is continually changing.  There is a
 * possibility that the ACP and ARP counts may change between the LO
 * and HI 8-bit reads performed by the PC.  To get around this, always
 * perform three reads (LO,HI,LO), and verify that the two LO bytes
 * are identical.  The bracketed HI byte will then be consistent with
 * the LO bits.
 */
#define RIMIO_ANTPOS_LO         0x1D	/* ACP[7:0] */
#define RIMIO_ANTPOS_HI         0x1E	/* ARP[3:0] ACP[11:8] */

/* ------------------------------
 * STC Map Selection
 *
 * Each 256K x 6-Bit STC Map is addressed by:
 * 
 *      10-bit range gate counter          Bits  9.. 0
 *       8-bit ACP counter                 Bits 17..10
 *
 * The RIM hardware supports up to eight STC maps simultaneously
 * resident in memory.  The selection of which map is currently active
 * is made with the following three registers.  Together, they define
 * a 3-bit number that selects one of the eight maps.
 */
#define RIMIO_STC_SEL0          0x20	/* STC Map selection bits.  These */
#define RIMIO_STC_SEL1          0x21	/*   define a 3-bit number that */
#define RIMIO_STC_SEL2          0x22	/*   selects one of eight maps. */

/* One of the following values should be written to each of the above
 * ports.  These define how each STC Map selection bit is derived.
 */
#define STC_SEL_ZERO               0	/* Zero */
#define STC_SEL_ONE                1	/* One */
#define STC_SEL_HIBEAM             2	/* ASR9 HI beam selection */
#define STC_SEL_CIRPOL             3	/* ASR9 Circular polarization */
#define STC_SEL_BCHAN              4	/* ASR9 "B" channel */

#define RIMIO_STC_CNT           0x23	/* STC Control Register */
#define STC_CNT_DATPH0             0	/*   Phase selection for output data */
#define STC_CNT_DATPH1             1
#define STC_CNT_DATPH2             2
#define STC_CNT_CLKPH0             3	/*   Phase selection for output clock */
#define STC_CNT_CLKPH1             4
#define STC_CNT_CLKPH2             5

/* ------------------------------
 * ASR9 RF Switch Status and Control.
 *
 * The present sense of all switch and status inputs can be detected
 * using the RIMIO_DGSTS mechanism.  In addition, the real input level
 * may be replaced with a simulated level that is either low or high.
 */
#define RIMIO_SWSTS_SIMMASK     0x24	/* Mask of inputs to be simulated */
#define RIMIO_SWSTS_SIMDATA     0x25	/* Simulated input levels */

#define SWSTS_SW103                0	/*   Switch #103 */
#define SWSTS_SW104                1	/*   Switch #104 */
#define SWSTS_SW106                2	/*   Switch #106 */
#define SWSTS_AHI                  3	/*   A channel, HI beam */
#define SWSTS_BHI                  4	/*   B channel, HI beam */
#define SWSTS_LINPOL               5	/*   Linear polarization */
#define SWSTS_CHANB                6	/*   Channel B selected */
#define SWSTS_HIBIT                6	/*     (Highest bit defined) */

/* Likewise, the switches that are controlled by the RIM are also read
 * back via RIMIO_DGSTS.  The switch outputs are generally under the
 * control of internal RIM algorithms, but the lines may also be
 * forced to low or high simulated levels.
 */
#define RIMIO_SWCNT_SIMMASK     0x26	/* Mask of outputs to be simulated */
#define RIMIO_SWCNT_SIMDATA     0x27	/* Simulated output levels */

#define SWCNT_SW103                0	/*   Switch #103 */
#define SWCNT_SW104                1	/*   Switch #104 */
#define SWCNT_BEAMS                2	/*   Beam selection */
#define SWCNT_HIBIT                2	/*     (Highest bit defined) */

/* The switch pair 103/104 has only three well defined composite
 * states, which are interpreted as follows.
 */
#define SW103104_LIN_LO            0	/* Linear polarized, Low beam */
#define SW103104_LIN_HI            1	/* Linear polarized, High beam */
#define SW103104_CIRCULAR          2	/* Circular polarized */

/* ------------------------------
 * RIN-PE Data Stream Control
 *
 * These bits allow the RIN-PE interface to be started and stopped in
 * an orderly manner.  The user's start/stop request is written to the
 * read/write RINPE_CSR_RUNREQ bit, which is initially cleared on
 * powerup.  Setting RINPE_CSR_RUNREQ causes the RIN-PE data stream to
 * startup on the next radar pulse; clearing the bit causes the data
 * stream to shutdown at the end of the current pulse.  Full header
 * and data pulse sequences are guaranteed to be output in all cases
 * of starting and stopping.
 *
 * The readonly RINPE_CSR_RUNSTS bit indicates that the data stream is
 * running right now.  The correct procedure for shutting down the
 * RIN-PE interface is to clear RINPE_CSR_RUNREQ, and then wait for
 * CSR_RUNSTS to also become clear.
 */
#define RIMIO_RINPE_CSR         0x28	/* RIN-PE Control/Status Register */
#define RINPE_CSR_RUNREQ           0	/*   Request to run the data stream */
#define RINPE_CSR_RUNSTS           1	/*   Data stream is running now */

/* The following variable sets the delay in (quarter-bin units)
 * between the arrival of PRETO and the generation of the SYNC word in
 * the RIN-PE output data stream.  This constant is determined by
 * experiment, using the ASR9 itself and a test target at known
 * range.
 */
#define PEQBIN_SYNC               45	/* Delay to RIN-PE SYNC word */

/* ------------------------------
 * RVP7 Support Functions
 *
 * HardReset: The RVP7 external reset pin will be pulsed whenever the
 * ISA bus itself is reset, or whenever a "1" is written to the
 * RVP7CSR_HARDRESET bit.  Note that the RVP7 requires approximately 2.0
 * seconds to complete its self tests after being reset.  No SCSI I/O
 * should be attempted during that time.
 */
#define RIMIO_RVP7CSR           0x29    /* RVP7 Control/Status Register */
#define RVP7CSR_HARDRESET          0    /*   Pulse the external reset line */


/* ******************************************
 * *                                        *
 * * Diagnostic Input and Output Monitoring *
 * *                                        *
 * ******************************************
 *
 * These I/O ports assist in the creation of semi-automated procedures
 * for checking out RIM boards and chassis in a production
 * environment.  Through these ports, all external input and output
 * lines can be directly monitored, and all output lines can be set to
 * a known state.
 *
 * To economize on the allocation of port address space, the
 * diagnostic functions are handled one bit at a time through the
 * RIMIO_DGSTS and RIMIO_DGOUT locations.  This approach uses only two
 * I/O ports, rather than potentially as many as ten (which would be
 * one sixth of the total).
 */

/* ------------------------------
 * Diagnostic Output Control
 *
 * These are the external output signals that can be forced to either
 * a high or low state.  A given output is set by writing RIMIO_DGOUT
 * with the signal's select code merged with the desired state of the
 * line in DGOUT_DATA.  Only one output can be forced at a time.
 *
 * When a nonzero select code is written, then the selected output
 * line will take on the indicated data level.
 */
#define RIMIO_DGOUT             0x3A	/* Diagnostic outputs */
#define DGOUT_DATA                 7	/*   Output data bit is here */

#define DGOUT_WP6WXTD              1
#define DGOUT_WP6WXCK              2
#define DGOUT_WPCX103              3
#define DGOUT_WPCX104              4
#define DGOUT_WPBEAMS              5
#define DGOUT_WPSTC00              6
#define DGOUT_WPSTC01              7
#define DGOUT_WPSTC02              8
#define DGOUT_WPSTC03              9
#define DGOUT_WPSTC04             10
#define DGOUT_WPSTC05             11
#define DGOUT_WPSTCLK             12
#define DGOUT_PEDAT00             13
#define DGOUT_PEDAT01             14
#define DGOUT_PEDAT02             15
#define DGOUT_PEDAT03             16
#define DGOUT_PEDAT04             17
#define DGOUT_PEDAT05             18
#define DGOUT_PEDAT06             19
#define DGOUT_PEDAT07             20
#define DGOUT_PEDAT08             21
#define DGOUT_PEDAT09             22
#define DGOUT_PEDAT10             23
#define DGOUT_PEDAT11             24
#define DGOUT_PEDAT12             25
#define DGOUT_PEDAT13             26
#define DGOUT_PEDAT14             27
#define DGOUT_PEDAT15             28
#define DGOUT_PESYNCN             29
#define DGOUT_PEVALDN             30
#define DGOUT_PEPHASE             31
#define DGOUT_PERXCLK             32
#define DGOUT_WPSPAR0             33
#define DGOUT_WPSPAR1             34
#define DGOUT_WPSPAR2             35
#define DGOUT_WPSPAR3             36

#define DGOUT_HI_LINENUM          36	/* Highest numbered output line */

/* ------------------------------
 * Diagnostic Status Monitor
 *
 * Input and output signal states can be read from RIMIO_DGSTS at any
 * time; the normal operation of the RIM will not be affected.  Signal
 * levels are obtained by first writing RIMIO_DGSTS with the signal's
 * select code, followed by reading the data bit in DGSTS_DATA.
 * Either "input" or "output" line select codes may be used.
 */
#define RIMIO_DGSTS             0x3B	/* Diagnostic status */
#define DGSTS_DATA                 7	/*   Returned data bit is here */

#define DGIN_WPALT00              37
#define DGIN_WPALT01              38
#define DGIN_WPALT02              39
#define DGIN_WPALT03              40
#define DGIN_WPALT04              41
#define DGIN_WPALT05              42
#define DGIN_WPALT06              43
#define DGIN_WPALT07              44
#define DGIN_WPALT08              45
#define DGIN_WPALT09              46
#define DGIN_WPALT10              47
#define DGIN_WPALT11              48
#define DGIN_WPPRETO              49
#define DGIN_WPRGATE              50
#define DGIN_WPACP                51
#define DGIN_WPARP                52
#define DGIN_WPSX103              53
#define DGIN_WPSX104              54
#define DGIN_WPSX106              55
#define DGIN_WPCHB                56
#define DGIN_WPLP                 57
#define DGIN_WPAHI                58
#define DGIN_WPBHI                59
#define DGIN_PESPNDN              60
#define DGIN_PENRDYN              61
#define DGIN_WPSPAR0              62
#define DGIN_WPSPAR1              63
#define DGIN_WPSPAR2              64
#define DGIN_WPSPAR3              65

#define DGIN_HI_LINENUM           65	/* Highest numbered input line */

/* The following clock input signal monitor selections are defined in
 * the same way as all others, but they can not be used with the
 * RIMIO_DGSTS port.  These definitions are only interpreted by the
 * rim_get_line_state() API routine.
 */
#define DGIN_WP013MH             125
#define DGIN_WP026MH             126
#define DGIN_WP103MH             127

/* *************************************
 * *                                   *
 * * Oscilloscope Test Point Selectors *
 * *                                   *
 * *************************************
 *
 * There are many internal and external signals in the RIM and it
 * would be impractical to try to have test points for them all.
 * Rather, TP_COUNT scope test points are supplied, each of which has
 * a connection to both programmable PLDs (U1 and U2).  Up to TP_COUNT
 * channels of a multi-trace scope may be clipped onto these test
 * points, and the signals to view are selected in software.  You
 * never have to move the scope probes; simply hook them up once, and
 * then select what you want to view.
 */
#define RIMIO_TP0               0x3C	/* Test point #0 selection */
#define RIMIO_TP1               0x3D	/* Test point #1 selection */
#define RIMIO_TP2               0x3E	/* Test point #2 selection */
#define RIMIO_TP3               0x3F	/* Test point #3 selection */

#ifdef RIMIODEF_WSR88D
#define TP_COUNT_IQD               3    /* Number of test points on iqdata */
#define TP_COUNT_MAS               2    /*   and master chips. */

/* ------------------------------
 * The following signals are sourced by U1.  All of these codes must
 * have the 80H bit clear.  In addition to their primary output on a
 * group of the RINPE data lines, the first two test points are driven
 * onto the onboard testpoint pins.
 */
#define TPU1_TRIG1              0x01    /* RVP7 Trigger #1 */
#define TPU1_TRIG2              0x02    /* RVP7 Trigger #2 */
#define TPU1_TRIG3              0x03    /* RVP7 Trigger #3 */
#define TPU1_TRIG4              0x04    /* RVP7 Trigger #4 */
#define TPU1_TRIG5              0x05    /* RVP7 Trigger #5 */
#define TPU1_TRIG6              0x06    /* RVP7 Trigger #6 */
#define TPU1_TRIG7              0x07    /* RVP7 Trigger #7 */
#define TPU1_TRIG8              0x08    /* RVP7 Trigger #8 */
#define TPU1_TRIG9              0x09    /* RVP7 Trigger #9 */
#define TPU1_TRIG10             0x0A    /* RVP7 Trigger #10 */

#define TPU1_RFGATE             0x0B    /* WSR88D RF_GATE */
#define TPU1_PLSTART            0x0C    /* WSR88D RF_PULSE_START */
#define TPU1_MODDIS             0x0D    /* WSR88D MOD_DISCHARGE */
#define TPU1_MODCHG             0x0E    /* WSR88D MOD_CHARGE */
#define TPU1_FILRES             0x0F    /* WSR88D FILAMENT_RESET */
#define TPU1_RFDRIVE            0x10    /* WSR88D RF_DRIVE */
#define TPU1_POSTCHG            0x11    /* WSR88D POST_CHARGE */
#define TPU1_TRIGCHG            0x12    /* WSR88D TRIGGER_CHARGE */
#define TPU1_PROTCMD            0x13    /* WSR88D RCVR_PROTECT_CMD */
#define TPU1_PROTRSP            0x14    /* WSR88D RCVR_PROTECT_RSP */
#define TPU1_CATHODE            0x15    /* WSR88D CATHODE_PULSE */
#define TPU1_SHORTRF            0x16    /* WSR88D SHORT_RF_PULSE */
#define TPU1_SHORTBM            0x17    /* WSR88D SHORT_BEAM_PULSE */
#define TPU1_PRATE0             0x18    /* WSR88D PULSE_RATE_INTERVAL[0] */
#define TPU1_PRATE1             0x19    /* WSR88D PULSE_RATE_INTERVAL[1] */
#define TPU1_PRATE2             0x1A    /* WSR88D PULSE_RATE_INTERVAL[2] */
#define TPU1_REFCLK             0x1B    /* WSR88D 9.59MHz reference */

#define TPU1_10MHZ              0x1C    /* 10MHz free running reference */

#else /* #ifdef RIMIODEF_WSR88D */
#define TP_COUNT                   2	/* Number of test points */
/* ------------------------------
 * The following signals are sourced by U1.  All of these codes must
 * have the 80H bit clear.
 */
#define TPU1_WP103MHD           0x01	/* 10.3MHz ASR9 clock */
#define TPU1_WP026MHD           0x02	/*  2.6MHz ASR9 clock */
#define TPU1_WP013MHD           0x03	/*  1.3MHz ASR9 clock */
#define TPU1_PCBCLK             0x04	/* ISA bus system clock */

#define TPU1_WPALT00            0x05	/* ASR9 I/Q data bit 0 */
#define TPU1_WPALT11            0x06	/* ASR9 I/Q data bit 11 */

#define TPU1_IBDCLK             0x07	/* RVP7 I/Q clock */
#define TPU1_IBDCLR             0x08	/* RVP7 I/Q reset */
#define TPU1_IBD00              0x09	/* RVP7 I/Q data bit 0 */
#define TPU1_IBD15              0x0A	/* RVP7 I/Q data bit 15 */
#define TPU1_IBD16              0x0B	/* RVP7 I/Q data bit 16 */
#define TPU1_IBD17              0x0C	/* RVP7 I/Q data bit 17 */

#define TPU1_TGEN4              0x0D	/* RVP7 Trigger generator #4 */
#define TPU1_TGEN5              0x0E	/* RVP7 Trigger generator #5 */
#define TPU1_INTRIG             0x0F	/* RVP7 Trigger source */

#define TPU1_PESPNDN            0x10	/* RIN-PE suspend */
#define TPU1_PENRDYN            0x11	/* RIN-PE not-ready */
#define TPU1_PERXCLK            0x12	/* RIN-PE data clock */
#define TPU1_PEPHASE            0x13	/* RIN-PE data phase */
#define TPU1_PESYNCN            0x14	/* RIN-PE sync */
#define TPU1_PEVALDN            0x15	/* RIN-PE valid */
#define TPU1_PEDAT00            0x16	/* RIN-PE data bit 0 */
#define TPU1_PEDAT15            0x17	/* RIN-PE data bit 15 */

#define TPU1_IQSAMP0            0x18	/* Sampling points #1 and #2 for ASR9 */
#define TPU1_IQSAMP1            0x19	/*  (rising) and RVP7 (falling) data. */

#define TPU1_WPACP              0x1A	/* ASR9 antenna control pulse */
#define TPU1_WPARP              0x1B	/* ASR9 antenna reset pulse */
#define TPU1_AZ0000             0x1C	/* Low four bits of AZ are zero */

#define TPU1_HIBEAM             0x1D	/* HI beam indicator, delayed */

#endif /* #ifdef RIMIODEF_WSR88D */

/* ------------------------------
 * The following signals are sourced by U2.  All of these codes must
 * have the 80H bit set.
 */
#define TPU2_013MID             0x81	/* Mid point of 1.3MHz data */
#define TPU2_013END             0x82	/* End point of 1.3MHz data */

#define TPU2_WP6WXCLK           0x83	/* ASR9 serial clock */
#define TPU2_WP6WXTD            0x84	/* ASR9 serial transmit data */

#define TPU2_WPSTCLK            0x85	/* ASR9 STC clock */
#define TPU2_WPSTC00            0x86	/* ASR9 STC data bit 0 */
#define TPU2_WPSTC05            0x87	/* ASR9 STC data bit 5 */

#define TPU2_WPGATEO            0x88	/* ASR9 range gate */
#define TPU2_WPPRETO            0x89	/* ASR9 pretrigger */
#define TPU2_WPAHI              0x8A	/* ASR9 "A" Hi beam */
#define TPU2_WPBHI              0x8B	/* ASR9 "B" Hi beam */
#define TPU2_WPLP               0x8C	/* ASR9 linear polarization */
#define TPU2_WPCHB              0x8D	/* ASR9 Chan "B" */

#define TPU2_WPCX103            0x8E	/* ASR9 switch 103 control */
#define TPU2_WPSX103            0x8F	/* ASR9 switch 103 sense */
#define TPU2_WPCX104            0x90	/* ASR9 switch 104 control */
#define TPU2_WPSX104            0x91	/* ASR9 switch 104 sense */
#define TPU2_WPSX106            0x92	/* ASR9 switch 106 sense */
#define TPU2_WPBEAMS            0x93	/* ASR9 beam select */

/* *****************************
 * *                           *
 * * Static I/O RAM Memory Map *
 * *                           *
 * *****************************
 */
#define RIMEM_SIZE          0x400000	/* RAM Size (4-MBytes) */

/* ------------------------------
 * STC Map definitions
 */
#define RIMEM_STCMAP_BASE   0x000000	/* STC Map base address */

#define RIMEM_STCMAP_SECTORS     256	/* 256 sectors per 360 degrees */
#define RIMEM_STCMAP_SECTSIZE   1024	/* 1024 range cells (1.3 MHz clocks) */
#define RIMEM_STCMAP_SIZE  (RIMEM_STCMAP_SECTORS * RIMEM_STCMAP_SECTSIZE)

#define RIMEM_STCMAP_NUM           8	/* Number of STC Maps */

/* Location of the Nth STC Map
 */
#define RIMEM_STCMAP(N) (RIMEM_STCMAP_BASE + ((N) * RIMEM_STCMAP_SIZE))

/* ------------------------------
 * Allocations for serial bitstream output.  RIMEM_SO_SIZE is the
 * maximum length (in bits) of the Data-Plus-STOP portion of any
 * single transmission.
 */
#define RIMEM_SO_SIZE_BITS      10
#define RIMEM_SO_SIZE     (1 << RIMEM_SO_SIZE_BITS)

#define RIMEM_SO_DATABUF0   0x200000	/* Data Buffer #0 address */
#define RIMEM_SO_IDLEBUF    0x202000	/* Idle Buffer */

/* Location of the Nth Serial Data Buffer
 */
#define RIMEM_SO_BUF(N) (RIMEM_SO_DATABUF0 + ((N) * RIMEM_SO_SIZE))

/* ------------------------------
 * The internal simulator for PRETO (ASR9 Pretrigger) uses an array of
 * desired time intervals between successive PRETO pulses.  These time
 * intervals are measured as 14-bit counts of the 1.3MHz clock.  The
 * counts reside in the lower fourteen bits of a 16-bit word, which is
 * then stored at pairs of memory bytes; the low byte of each 16-bit
 * value occupying the lower address of the pair.
 */
#define RIMEM_PRETO_SIMTAB  0x204000	/* Base of simulated trigger times */

/* The end of the sequence of time intervals is controlled by a 2-bit
 * code in the upper bits of each 16-bit word.  The ending condition
 * may be forced, or it may depend on the state of other signals
 * within the RIM.  This allows PRETO to sync up with other logic.  In
 * all cases, the ending condition applies AFTER the completion of the
 * simulated period contained in the low part of the 16-bit word.
 *
 * A maximum of 64 successive time intervals can be specified.  If no
 * explicit end is found in the first 64 slots, the simulator will
 * wrap around to the beginning of the table anyway.
 */
#define PRETO_CODE_CONTINUE         0	/* Normal continuation */
#define PRETO_CODE_END              1	/* End of list */
#define PRETO_CODE_ACP16X           2	/* End if the antenna angle has passed */
					/*   through a multiple of 16. */
/* ------------------------------
 * The internal simulator for ASR9 and RVP7 (I,Q) read preloaded 8-bit
 * values into the most significant bits of each data sample.
 */
#define RIMEM_ASR9_SIMIQ    0x205000	/* Base of 2048 pairs of simulated */
#define RIMEM_RVP7_SIMIQ    0x206000	/*   (I,Q) data bytes */

#endif /* #ifndef RIMIODEF_H */
