/* **********************************************************************
 * *                                                                    *
 * *      RDA System PCI Board 'Softplane' Driver Layer Definitions     *
 * *                                                                    *
 * **********************************************************************
 * File: include/softplane_lib.h
 *
 *                       COPYRIGHT (c) 2003  BY
 *          SIGMET INCORPORATED, WESTFORD MASSACHUSETTS, U.S.A.
 * 
 * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
 * ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
 * INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
 * COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
 * OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
 * TRANSFERED.
 */
#ifndef SIGMET_SOFTPLANE_LIB_H
#define SIGMET_SOFTPLANE_LIB_H 1

/* = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 * The SPL driver library entry points deal with interconnections
 * between PCI boards, as well as the I/O pin assignments on each
 *                      individual board.
 * = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 */

/* *******************************
 * *                             *
 * * Message Catalog Definitions *
 * *                             *
 * *******************************
 */

#define     PINCONFLICT       1
#define SPL_PINCONFLICT      (SPL_FACILITY + PINCONFLICT)

#ifndef MESSAGE_ONLY

/* **********************************************
 * *                                            *
 * *  Softplane Physical Electrical Interfaces  *
 * *                                            *
 * **********************************************
 */
#define SPLPINNAMELEN 24
#define SPLPINDEF( PINNAME ) char PINNAME[ SPLPINNAMELEN ]

struct splB2B {			/* Board-to-Board serial bits */
  SPLPINDEF( bit00 ) ; SPLPINDEF( bit01 ) ; SPLPINDEF( bit02 ) ;
  SPLPINDEF( bit03 ) ; SPLPINDEF( bit04 ) ; SPLPINDEF( bit05 ) ;
  SPLPINDEF( bit06 ) ; SPLPINDEF( bit07 ) ;
} ;
#if IO62B2B_NBITS != 8
#error Please manually maintain all B2B definitions in this file
#endif

/* ------------------------------
 * Definitions for direct hookup pins on the IO62 PCI card.
 */
struct splIoLinePair {		/* Electrical properties of one pair of lines */
  UINT1 lRS422 ;		/*   RS422 (else TTL/CMOS) */
  SINT1 iTerm ;			/*   Termination (0:None, +1:PullUp, -1:PullDn */
  char  pad2x2[2] ;
  SPLPINDEF( pinPos ) ;		/*   Positive pin */
  SPLPINDEF( pinNeg ) ;		/*   Negative pin */
} ;

struct splIo62Assembly {	/* A complete stand-alone IO62 assembly */
  struct splIoLinePair io[20] ;	/*   The set of reconfigurable line pairs */

  SPLPINDEF( TxPhaseLines ) ;	/*   Optional output of transmit phase */
#define SPLTXPHZ_IO4TO11 "I/O:4-11"

  SPLPINDEF( SharedStsModel ) ;	/*   Model for shared status lines */
#define SPLSHMOD_TDWR_V1 "MIT/LL-TDWR-V1"

  SPLPINDEF( ioSerial0_TxRx ) ; /*   Hookup of generic serializer */
#define SPLSERIAL0_TTY0      "TTY0"
#define SPLSERIAL0_RX12_TX16 "Rx:12/Tx:16"

  SPLPINDEF( Relay1 ) ;		/*   On-board relays */
  SPLPINDEF( Relay2 ) ;

  SPLPINDEF( TTY0_Tx ) ;	/*   RS232 TTY transmitters/Receivers */
  SPLPINDEF( TTY1_Tx ) ;
  SPLPINDEF( TTY0_Rx ) ;
  SPLPINDEF( TTY1_Rx ) ;

  SPLPINDEF( Trig0 ) ;		/*   12V Trigger drivers */
  SPLPINDEF( Trig1 ) ;
  SPLPINDEF( Trig2 ) ;
  SPLPINDEF( Trig3 ) ;

  struct splB2B TxB2B ;		/*   Board-to-Board serial transmitter */
  struct splB2B RxB2B ;		/*     and receiver. */
} ;

/* ------------------------------
 * Definitions for the pins on the IO62CP general purpose connector
 * panel which is generally plugged into each IO62 PCI card.
 */
struct splCpDb25GpTTL {		/* General purpose TTL connector */
  SPLPINDEF( pin01 ) ; SPLPINDEF( pin02 ) ; SPLPINDEF( pin03 ) ;
  SPLPINDEF( pin04 ) ; SPLPINDEF( pin05 ) ; SPLPINDEF( pin06 ) ;
  SPLPINDEF( pin07 ) ; SPLPINDEF( pin08 ) ; SPLPINDEF( pin09 ) ;
  SPLPINDEF( pin10 ) ; SPLPINDEF( pin11 ) ; SPLPINDEF( pin12 ) ;
  SPLPINDEF( pin13 ) ; SPLPINDEF( pin14 ) ; SPLPINDEF( pin15 ) ;
  SPLPINDEF( pin16 ) ; SPLPINDEF( pin17 ) ; SPLPINDEF( pin18 ) ;
  SPLPINDEF( pin19 ) ; SPLPINDEF( pin20 ) ;
} ;

struct splCpAssembly {		/* A complete connector panel assembly */
  struct splCpDb25GpTTL J1 ;	/* General purpose TTL/CMOS */
  struct splCpDb25GpTTL J2 ;
  struct splCpDb25GpTTL J4 ;
  struct splCpDb25GpTTL J5 ;
  struct splCpDb25GpTTL J7 ;

  struct splIoLinePair J3_01_14 ; /* Eight IO62 connections to J3 */
  struct splIoLinePair J3_02_15 ;
  struct splIoLinePair J3_03_16 ;
  struct splIoLinePair J3_04_17 ;
  struct splIoLinePair J3_05_18 ;
  struct splIoLinePair J3_06_19 ;
  struct splIoLinePair J3_07_20 ;
  struct splIoLinePair J3_08_21 ;
  SPLPINDEF( J3_09_22 ) ;	/* Additional 'DG' RS-422 Tx/Rx chips */
  SPLPINDEF( J3_10_23 ) ;

  struct splIoLinePair J9_01_14 ; /* Seven IO62 connections to J9 */
  struct splIoLinePair J9_02_15 ;
  struct splIoLinePair J9_03_16 ;
  struct splIoLinePair J9_04_17 ;
  struct splIoLinePair J9_05_18 ;
  struct splIoLinePair J9_06_19 ;
  struct splIoLinePair J9_07_20 ;

  SPLPINDEF( TxPhaseLines ) ;	/* Optional output of transmit phase */
  SPLPINDEF( SharedStsModel ) ;	/* Model for shared status lines */
  SPLPINDEF( ioSerial0_TxRx ) ; /* Hookup of generic serializer */

  SPLPINDEF( J6_IntRelay1 ) ;	/* Internal/External relay outputs on J6 */
  SPLPINDEF( J6_IntRelay2 ) ;
  SPLPINDEF( J6_IntRelay3 ) ;
  SPLPINDEF( J6_ExtRelay1 ) ;
  SPLPINDEF( J6_ExtRelay2 ) ;
  SPLPINDEF( J6_ExtRelay3 ) ;
  SPLPINDEF( J6_ExtRelay4 ) ;

  SPLPINDEF( J13_BNC ) ;	/* BNC testpoint monitors */
  SPLPINDEF( J16_BNC ) ;

  SPLPINDEF( J14_BNC ) ;	/* BNC triggers from IO62 */
  SPLPINDEF( J15_BNC ) ;
  SPLPINDEF( J17_BNC ) ;
  SPLPINDEF( J18_BNC ) ;

  SPLPINDEF( TTY0_Tx ) ;	/* RS232 TTY Tx/Rx on IO62 */
  SPLPINDEF( TTY1_Tx ) ;
  SPLPINDEF( TTY0_Rx ) ;
  SPLPINDEF( TTY1_Rx ) ;

  SPLPINDEF( Relay1 ) ;		/* Relays on IO62 */
  SPLPINDEF( Relay2 ) ;
} ;

/* ------------------------------
 * Physical configuration of the standard remote backpanel for the
 * MIT/LL TDWR application.
 */
struct splTdwrV1Assembly {	/* The programmable portion of the panel */
  struct splCpDb25GpTTL J1 ;	/* General purpose TTL/CMOS */
  struct splCpDb25GpTTL J2 ;
  struct splCpDb25GpTTL J4 ;
  struct splCpDb25GpTTL J5 ;
  struct splCpDb25GpTTL J7 ;

  struct splIoLinePair J3_01_14 ; /* Eight IO62 connections to J3 */
  struct splIoLinePair J3_02_15 ;
  struct splIoLinePair J3_03_16 ;
  struct splIoLinePair J3_04_17 ;
  struct splIoLinePair J3_07_20 ;
  struct splIoLinePair J3_08_21 ;
  SPLPINDEF( J3_09_22 ) ;	/* Additional 'DG' RS-422 Tx/Rx chips */
  SPLPINDEF( J3_10_23 ) ;

  SPLPINDEF( J14_BNC ) ;	/* BNC triggers from IO62 */
  SPLPINDEF( J15_BNC ) ;
  SPLPINDEF( J17_BNC ) ;
  SPLPINDEF( J18_BNC ) ;
} ;

/* ------------------------------
 * Physical configuration of the 'RVP8 portion' of the custom ORDA I/O
 * panel.  Most of the control lines are handled by logic internal to
 * the PCI card's FPGA, so very few entries appear here.
 */
struct splRvp88dAssembly {	/* The programmable portion of RVP88D */
  struct splIoLinePair spare1 ;	/*   Spare IO62 line pairs */
  struct splIoLinePair spare2 ;
  struct splIoLinePair spare3 ;
} ;

/* ------------------------------
 * Physical configuration of the 'RCP8 portion' of the custom ORDA I/O
 * panel.  The many dedicated TTL<->RS422 converters on the panel are
 * listed here as using their actual WSR88D signal names.
 */
struct splRcp88dAssembly {	/* The programmable portion of RCP88D */
  SPLPINDEF( phmodFail      ) ; SPLPINDEF( chanFail     ) ;
  SPLPINDEF( opFreqRefFl    ) ; SPLPINDEF( cohoRefFail  ) ;
  SPLPINDEF( dauOkay_       ) ; SPLPINDEF( dcuOkay_     ) ;
  SPLPINDEF( analogMux0     ) ; SPLPINDEF( analogMux1   ) ;
  SPLPINDEF( driveSig32dB   ) ; SPLPINDEF( driveSig40dB ) ;
  SPLPINDEF( driveSig8dB    ) ; SPLPINDEF( driveSig16dB ) ;
  SPLPINDEF( driveSig2dB    ) ; SPLPINDEF( driveSig4dB  ) ;
  SPLPINDEF( noiseCtrlIn    ) ; SPLPINDEF( driveSig1dB  ) ;
  SPLPINDEF( rcpGoLed_      ) ; SPLPINDEF( p5Ion        ) ;
  SPLPINDEF( shortBeamPulse ) ; SPLPINDEF( shortRFPulse ) ;
  SPLPINDEF( drSigBit4      ) ; SPLPINDEF( drSigPos4    ) ;
  SPLPINDEF( drSigBit3      ) ; SPLPINDEF( drSigPos3    ) ;
  SPLPINDEF( drSigBit2      ) ; SPLPINDEF( drSigPos2    ) ;
  SPLPINDEF( drSigBit1      ) ; SPLPINDEF( drSigPos1    ) ;

  struct splIoLinePair spare1 ;	/*   Spare IO62 line pairs */
  struct splIoLinePair spare2 ;
  struct splIoLinePair spare3 ;
  struct splIoLinePair spare4 ;
  struct splIoLinePair spare5 ;

  struct splB2B TxB2B ;		/*   Board-to-Board serial transmitter */
  struct splB2B RxB2B ;		/*     and receiver. */
} ;

/* ------------------------------
 * Configuration of a set of four IO62 boards when used for testing
 * ORDA backpanel I/O.
 */
struct splOrdaPanelTest {	/* ORDA backpanel test setups */
  SINT4 iIo62UnitExtA ;		/*   IO62 unit number --> External Panel-A */
  SINT4 iIo62UnitExtB ;		/*   IO62 unit number --> External Panel-B */
  SINT4 iIo62UnitRvp8 ;		/*   IO62 unit number --> ORDA RVP8 connector */
  SINT4 iIo62UnitRcp8 ;		/*   IO62 unit number --> ORDA RCP8 connector */
  FLT4  fCathodeVolts ;		/*   Cathode threshold level in Volts */
} ;

/* ------------------------------
 * The top level softplane configuration file.
 */
struct splIo62Instance {	/* A single IO62 PCI card */
  UINT4 lInUse ;		/*   This card is being used */
  char sExtPanel[12] ;		/*   Type of backpanel that is attached */
#define SPLEXTP_DIRECT "Direct"	/*     Direct I/O with IO62 connector itself */
#define SPLEXTP_STDCP  "IO62CP"	/*     Standard IO62CP connector panel */
#define SPLEXTP_RVP88D "RVP88D"	/*     RVP8 portion of WSR88D panel */
#define SPLEXTP_RCP88D "RCP88D"	/*     RCP8 portion of WSR88D panel */
#define SPLEXTP_TDWRV1 "TDWRV1"	/*     MIT/LL TDWR custom code, standard panel */
  union {			/*   I/O depends on type of panel */
    struct splIo62Assembly   Io ;
    struct splCpAssembly     Cp ;
    struct splRvp88dAssembly Rvp88d ;
    struct splRcp88dAssembly Rcp88d ;
    struct splTdwrV1Assembly TdwrV1 ;
  } Opt ;
} ;
struct splConfig {		/* Top level softplane configuration */
  char sVersion[8] ;		/*   IRIS version when saved */
  struct splIo62Instance Io62[ IO62MAXUNITS ] ; /* IO62 boards + optional panels */
  struct splOrdaPanelTest OrdaPanelTest ;       /* ORDA panel tester hookups */
} ;

/* ***************************************
 * *                                     *
 * *  Softplane Logical I/O Definitions  *
 * *                                     *
 * ***************************************
 */

#define NSPL_CNTBYTES   10	/* # of auxiliary control bytes */
#define NSPL_STSBYTES   40	/* # of auxiliary status bytes */

#define SPLINVCHR   '~'		/* Signal inversion prefix character */

/* ------------------------------
 * Logical output signals.  These are the clean internal form of all
 * signals that can be driven as electrical outputs.
 */
struct splLogicCnt {
  /* Antenna angles in parallel output form.
   */
  BIN2   iPedAZ,   iPedEL ;	/* Pedestal AZ/EL */
  BIN2 iEarthAZ, iEarthEL ;	/* Earth AZ/EL */

  /* Antenna/Pedestal/Servo control signals
   */
  UINT1 lServoPwr ;		/* Servo amplifier power */
  UINT1 lCabRelay ;		/* Traditional servo 'Cabinet relay' */

  /* Radar Transmitter/Receiver control signals
   */
  UINT1 lTransmitPwr ;		/* Transmitter power */
  UINT1 iPWidth ;		/* Pulsewidth control bits */
  UINT1 lTrigBlank ;		/* Trigger blanking command */

  UINT1 lRadiateOn ;		/* Radiate On/Off control */
  UINT1 lRadiateOff ;

  /* Noise source and test signal generator
   */
  UINT1 lNoiseGenOn ;		/* RF noise source On/Off */
  UINT1 lSigGenOn ;		/* RF signal generator On/Off, */
  UINT1 lSigGenCW ;		/*   continuous wave (versus pulsed), */
  SINT2 iSigGenLevel ;		/*   and output power level. */

  /* Miscellaneous system control signals
   */
  UINT1 lReset ;		/* External equipment reset */
  UINT1 iIrisMode ;		/* IRIS mode select bits */

  UINT1 iAux[ NSPL_CNTBYTES ] ;	/* Auxiliary control bytes */

  UINT1 lStepCntAZ, lStepUpAZ ;	/* Stepper motor "count" pulses and "up" */
  UINT1 lStepCntEL, lStepUpEL ;	/*   direction indicator. */

  UINT1 lTrue, lFalse ;		/* Fixed Hi/Lo bits */
  char  pad38x2[2] ;
} ;

#define SPLLOGICCNT_INITIALIZER \
  { {    "cPedAZ[15:0]", LOGICCNTBIT( iPedAZ       ) }, \
    {    "cPedEL[15:0]", LOGICCNTBIT( iPedEL       ) }, \
    {  "cEarthAZ[15:0]", LOGICCNTBIT( iEarthAZ     ) }, \
    {  "cEarthEL[15:0]", LOGICCNTBIT( iEarthEL     ) }, \
    {       "cServoPwr", LOGICCNTBIT( lServoPwr    ) }, \
    {   "cCabinetRelay", LOGICCNTBIT( lCabRelay    ) }, \
    {    "cTransmitPwr", LOGICCNTBIT( lTransmitPwr ) }, \
    {    "cPWidth[3:0]", LOGICCNTBIT( iPWidth      ) }, \
    {      "cTrigBlank", LOGICCNTBIT( lTrigBlank   ) }, \
    {      "cRadiateOn", LOGICCNTBIT( lRadiateOn   ) }, \
    {     "cRadiateOff", LOGICCNTBIT( lRadiateOff  ) }, \
    {     "cNoiseGenOn", LOGICCNTBIT( lNoiseGenOn  ) }, \
    {       "cSigGenOn", LOGICCNTBIT( lSigGenOn    ) }, \
    {       "cSigGenCW", LOGICCNTBIT( lSigGenCW    ) }, \
    {    "cSigGen[7:0]", LOGICCNTBIT( iSigGenLevel ) }, \
    {          "cReset", LOGICCNTBIT( lReset       ) }, \
    {  "cIrisMode[2:0]", LOGICCNTBIT( iIrisMode    ) }, \
    {      "cAux[80:0]", LOGICCNTBIT( iAux         ) }, \
    {      "cStepCntAZ", LOGICCNTBIT( lStepCntAZ   ) }, \
    {      "cStepCntEL", LOGICCNTBIT( lStepCntEL   ) }, \
    {       "cStepUpAZ", LOGICCNTBIT( lStepUpAZ    ) }, \
    {       "cStepUpEL", LOGICCNTBIT( lStepUpEL    ) }, \
    {            "true", LOGICCNTBIT( lTrue        ) }, \
    {           "false", LOGICCNTBIT( lFalse       ) }, \
    {              NULL, 0                           } }

#if NSPL_CNTBYTES != 10
#error Please fix static initializer for AUX control bytes
#endif

/* Definitions and initializer for internally generated control
 * signals.
 */
#define SPLINTERNAL 0x00010000 /* Flag for internal signal */
#define SPLINTERNAL_TRIGGER0 (SPLINTERNAL +   0) /* User trigger outputs */
#define SPLINTERNAL_POLAR0   (SPLINTERNAL + 100) /* Polarization trigger outputs */

#define SPLINTERNAL_INITIALIZER \
  { { "trigger[12:1]", SPLINTERNAL_TRIGGER0 }, \
    {    "polar[2:1]", SPLINTERNAL_POLAR0   }, \
    {            NULL, 0                    } }

/* ------------------------------
 * Logical input signals.  These are the clean internal form of all
 * signals that can be received as electrical inputs.
 */
struct splLogicSts {
  /* Antenna angles in parallel input form.
   */
  BIN2 iPedAZ, iPedEL ;		/* Pedestal AZ/EL */

  /* Antenna/Pedestal/Servo status signals
   */
  UINT1 lServoPwr ;		/* Servo amplifier power */
  UINT1 lLocal, lStandby ;	/* External local & standby requests */
  UINT1 lLowerEL, lUpperEL ;	/* Elevation Lo/Hi limit switches */
  UINT1 lProxSwAZ, lProxSwEL ;	/* Proximity sensors for AZ/EL */

  /* Radar Transmitter/Receiver status signals
   */
  UINT1 lTransmitPwr ;		/* Transmitter power */
  UINT1 lTransmitLocal ;	/* Transmitter in local control */
  UINT1 iPWidth ;		/* Pulsewidth status bits */
  UINT1 lTrigBlank ;		/* Trigger blanking request */

  UINT1 lRadiate ;		/* Radiate is On */
  UINT1 lAirflowFlt ;		/* Airflow fault */
  UINT1 lWavegpFlt ;		/* Waveguide pressure fault */
  UINT1 lInterlockFlt ;		/* Safety interlock fault */
  UINT1 lMagCurrentFlt ;	/* Magnetron current fault */

  /* Noise source and test signal generator
   */
  char pad20x1[1] ;
  UINT1 lNoiseGenOn ;		/* RF noise source On/Off */
  UINT1 lSigGenOn ;		/* RF signal generator On/Off, */
  UINT1 lSigGenCW ;		/*   continuous wave (versus pulsed), */
  SINT2 iSigGenLevel ;		/*   output power level, */
  UINT1 lSigGenFlt ;		/*   and fault condition. */

  /* Miscellaneous system status signals
   */
  UINT1 lReset ;		/* External reset request */
  UINT1 iIrisMode ;		/* IRIS mode select bits */

  UINT1 iAux[ NSPL_STSBYTES ] ;	/* Auxiliary status bytes */
  char pad69x3[3] ;
} ;

#define SPLLOGICSTS_INITIALIZER \
  { {    "sPedAZ[15:0]", LOGICSTSBIT( iPedAZ         ) }, \
    {    "sPedEL[15:0]", LOGICSTSBIT( iPedEL         ) }, \
    {       "sServoPwr", LOGICSTSBIT( lServoPwr      ) }, \
    {          "sLocal", LOGICSTSBIT( lLocal         ) }, \
    {        "sStandby", LOGICSTSBIT( lStandby       ) }, \
    {        "sLowerEL", LOGICSTSBIT( lLowerEL       ) }, \
    {        "sUpperEL", LOGICSTSBIT( lUpperEL       ) }, \
    {       "sProxSwAZ", LOGICSTSBIT( lProxSwAZ      ) }, \
    {       "sProxSwEL", LOGICSTSBIT( lProxSwEL      ) }, \
    {    "sTransmitPwr", LOGICSTSBIT( lTransmitPwr   ) }, \
    {  "sTransmitLocal", LOGICSTSBIT( lTransmitLocal ) }, \
    {    "sPWidth[3:0]", LOGICSTSBIT( iPWidth        ) }, \
    {      "sTrigBlank", LOGICSTSBIT( lTrigBlank     ) }, \
    {        "sRadiate", LOGICSTSBIT( lRadiate       ) }, \
    {     "sAirflowFlt", LOGICSTSBIT( lAirflowFlt    ) }, \
    {      "sWavegpFlt", LOGICSTSBIT( lWavegpFlt     ) }, \
    {   "sInterlockFlt", LOGICSTSBIT( lInterlockFlt  ) }, \
    {  "sMagCurrentFlt", LOGICSTSBIT( lMagCurrentFlt ) }, \
    {     "sNoiseGenOn", LOGICSTSBIT( lNoiseGenOn    ) }, \
    {       "sSigGenOn", LOGICSTSBIT( lSigGenOn      ) }, \
    {       "sSigGenCW", LOGICSTSBIT( lSigGenCW      ) }, \
    {    "sSigGen[7:0]", LOGICSTSBIT( iSigGenLevel ) }, \
    {      "sSigGenFlt", LOGICSTSBIT( lSigGenFlt     ) }, \
    {          "sReset", LOGICSTSBIT( lReset         ) }, \
    {  "sIrisMode[2:0]", LOGICSTSBIT( iIrisMode      ) }, \
    {     "sAux[319:0]", LOGICSTSBIT( iAux           ) }, \
    {              NULL, 0                             } }

#if NSPL_STSBYTES != 40
#error Please fix static initializer for AUX status bytes
#endif

/* *************************
 * *                       *
 * *  Function Prototypes  *
 * *                       *
 * *************************
 */

/* The softplane information structure's actual contents are hidden
 * from the outside world at this point.  Only access should be
 * through the driver.
 */
struct spl_info ;
typedef struct spl_info SPL ;	/* Toplevel driver structure */

struct splPCICardCnt ;		/* Physical I/O structures, sometimes used */
struct splPCICardSts ;		/*   as I/O masks to increase efficiency. */
typedef struct splPCICardCnt splPhysCnt ;
typedef struct splPCICardSts splPhysSts ;

/* Structures for remapping bits.  The actual runtime remappings are
 * done via a list of splRemapBit structures.  This structure is kept
 * small so that the frequent remappings do not incurr a lot of cache
 * misses each time.  This requires that the larger (and infrequently
 * needed) auxiliary info be stored elsewhere.
 */
struct splRemapBit {		/* Map one bit into another */
  UINT2 iInOff, iOutOff ;	/*   Input and output bit offsets */
  UINT2 iInfoOff ;		/*   Offset of auxiliary information */
  UINT1 iInvert ;		/*   0x00 or 0xFF for normal/inverted */
  char pad7x1[1] ;
} ;
struct splRemapInfo {		/* AUX info (kept separate to help caching) */
  char sLogName[SPLPINNAMELEN] ;  /* Logical symbol name */
} ;

/* -------------------- spl_config.c --------------------
 */
SPL *splConfigure
( Rvp8Rx *Rx_a[ RX8MAXUNITS ], Rvp8Tx *Tx_a[ TX8MAXUNITS ],
  Io62  *Io_a[ IO62MAXUNITS ], MESSAGE *pStatus_a ) ;

const struct splConfig *splConfFile( const SPL *pSPL_a ) ;

SINT4 splConfigErrorCount( const SPL *pSPL_a ) ;

/* -------------------- spl_data.c --------------------
 */
struct splLogicCnt *splLogicCntTakeOwn( SPL *pSPL_a ) ;
const struct splLogicCnt *splLogicCntPeek( SPL *pSPL_a ) ;
void splLogicCntRelease( SPL *pSPL_a ) ;
void splLogicCntPhysIO( SPL *pSPL_a ) ;

void splLogicCntUsageMask( SPL *pSPL_a, struct splLogicCnt *pCnt_a ) ;

const struct splLogicSts *splLogicStsPhysIO
( SPL *pSPL_a, const splPhysSts *pPhysMask_a ) ;

const struct splLogicSts *splLogicStsPeek( SPL *pSPL_a ) ;

const splPhysSts *splPhysStsUsageMask
( SPL *pSPL_a, const struct splLogicSts *pSts_a ) ;

void splRemapAreaFwdBits
( volatile void *pIn_a, volatile void *pOut_a,
  struct splRemapBit *pMap_a, SINT4 nRemaps_a ) ;

void splRemapAreaRevMask
( volatile void *pIn_a, struct splRemapBit *pMap_a, SINT4 nRemaps_a ) ;

#endif /* #ifndef MESSAGE_ONLY */
#endif /* #ifndef SIGMET_SOFTPLANE_LIB_H */
