-- ********************************
-- *                              *
-- *   Port I/O Definitions for   *
-- * Radar Interface Module (RIM) *
-- *       (rimiodef.inc)         *
-- *                              *
-- ********************************

-- This file must be manually maintained in parallel with its C
-- companion file: rimiodef.h.  The syntax between C and AHDL is
-- too different to try to patch automatically.
--

-- The addressable port I/O space consists of 64 successive 8-bit
-- locations, beginning at the RIMIO_BASE base address.  The data bit
-- assignments are given below for each of the defined port addresses.
--
-- Generally, each port supports both read and write access via the
-- INP and OUTP opcodes.  This allows you to read the present contents
-- of a location so that individual bits can be modified.
--
-- Note that single-process access to the ports is generally assumed,
-- i.e., the operation of many ports assumes the consistency of
-- internal state between operations.  For example, the PLD external
-- memory is accessed by first setting up the RAM address, followed by
-- the actual read/write operations.  Clearly, this will not work
-- properly if the address is clobbered midway by another process.
--
-- There is a naming convention for these macros.  Port I/O
-- subaddresses have names of the form "RIMIO_xxxx", while the bits
-- pertaining to that port are named "xxxx_yyyy".  This reduces the
-- likelyhood of using the wrong bit definitions with a given port
-- address, because the "xxxx" part of the names need to match.

-- The I/O base address is kept within the basic 10-bit addressing
-- range of the PC.  This is because there is slightly better support
-- in LINUX for addressing I/O devices in this area.
--
CONSTANT RIMIO_BASE         = H"0140";	-- Base port I/O address
CONSTANT RIMIO_SPAN         = H"0040";	--   and overall span

CONSTANT RIMIO_SERIAL_INCL  = 2 ;	-- Serial number of this file

-- ***********************
-- *                     *
-- * Fixed PLD Functions *
-- *                     *
-- ***********************

-- The following functions are implemented primarily in the small
-- fixed PLD that can not be reprogrammed in the field.  As such,
-- these functions are kept to a minimum, and the assignments should
-- be viewed as more or less permanent.

-- ------------------------------
-- Top-Level Control and Status
--
-- The overall Control/Status register for the RIM ports is controlled
-- by the smaller PLD.  Its purpose is to disconnect the large PLDs
-- from the ISA bus during the times that their I/O signal pins are
-- undefined.  When TOPCSR_ALLOWIO is set, then ISA bus port I/O to
-- all addresses other than RIMIO_TOPCSR and RIMIO_JTAG will be passed
-- along to the large PLDs.
--
-- The small PLD enforces a 15usec maximum duration on the ISA "wait"
-- signal.  This is to prevent the bus (and LINUX) from hanging as a
-- result of an error in new PLD code.  If the 15usec is exceeded, the
-- the cycle is terminated and the TOPCSR_TIMEOUT bit is set.  That
-- bit can be manually cleared by writing a zero to it.
--
CONSTANT RIMIO_TOPCSR         = H"00";	-- Top-Level Control/Status
CONSTANT TOPCSR_ALLOWIO         =  0 ;	--   Allow I/O to all PLDs.
					--     (cleared on system reset)
CONSTANT TOPCSR_TIMEOUT         =  1 ;	--   ISA wait terminated after 15usec
CONSTANT TOPCSR_REV0            =  5 ;	--   Board revision level.
CONSTANT TOPCSR_REV1            =  6 ;	--     These read-only bits tell the
CONSTANT TOPCSR_REV2            =  7 ;	--     PC etch level (Rev.A,B,C, etc)

-- ------------------------------
-- JTAG Control Lines.
--
-- The two large PLDs are programmed in-circuit, and verified using a
-- common JTAG serial stream.  The JTAG lines are generated by the
-- smaller PLD that is programmed externally using a standard
-- programmer.  The ISP feature allows software upgrades of RIM code
-- to update the PLD contents as well.
--
-- Note that the JTAG loadup is handled by the Altera JAM Player
-- utility, which is compiled separately and run during (or
-- immediately after) the boot sequence of the PC.
--
CONSTANT RIMIO_PLDJTAG        = H"01";	-- JTAG Control Port
CONSTANT PLDJTAG_TDO            =  0 ;	--   TDO (Read Only)
CONSTANT PLDJTAG_TCK            =  1 ;	--   TCK (Write/Read)
CONSTANT PLDJTAG_TMS            =  2 ;	--   TMS (Write/Read)
CONSTANT PLDJTAG_TDI            =  3 ;	--   TDI (Write/Read)

-- ------------------------------
-- Sofware Controlled ISA Reset

-- Writing the magic number to this location is equivalent to the ISA
-- bus reset signal being asserted (at least, from the point of view
-- of the RIM PLDs).
--
CONSTANT RIMIO_PCRESET        = H"02";	-- Simulate ISA bus reset
CONSTANT PCRESET_MAGIC        = H"3C";	--   Magic number for reset

-- ------------------------------
-- ASR9 Clock Control
--
-- The three system clocks from the ASR9 (1.3, 2.6, and 10.3MHz) can
-- be replaced with locally generated clocks based on a 10MHz
-- oscillator.  This allows all of the RIM clock circuitry to
-- function, even when there is no external connection to the ASR9.
--
-- The phase of the 10.3MHz clock can be adjusted so that its edges
-- align properly with the 2.6MHz clock.  This is to compensate for
-- unknown cable delays in the ASR9<->RIM ribbon cables.  There are
-- three delay selection bits, and a readback register that shows a
-- snapshot of the 10.3MHz clock in the vicinity of the rising edge of
-- the 2.6MHz clock, sampled at approximately 7ns intervals.
--
-- The PC software should experiment with the delay settings until the
-- snapshot register shows the rising 10.3MHz clock transition
-- occuring close to time zero. Increasing the 3-bit delay shifts the
-- 10.3MHz clock "to the right", i.e., makes it later relative to the
-- 2.6Mhz rising edge.
--
CONSTANT RIMIO_CLKCNT         = H"03";	-- Clock Control
CONSTANT CLKCNT_SIMULATE        =  0 ;	--   Simulate ASR9 system clocks
CONSTANT CLKCNT_PHASE0          =  1 ;	--   1.3MHz simulated clock phase
CONSTANT CLKCNT_PHASE1          =  2 ;
CONSTANT CLKCNT_DELAY0          =  5 ;	--   Delay selection for 10.3MHz clock
CONSTANT CLKCNT_DELAY1          =  6 ;
CONSTANT CLKCNT_DELAY2          =  7 ;

CONSTANT RIMIO_CLKSNAP        = H"04";	-- Clock sampling snapshot
CONSTANT CLKSNAP_TP3            =  0 ;	--   Time +3
CONSTANT CLKSNAP_TP2            =  1 ;	--   Time +2
CONSTANT CLKSNAP_TP1            =  2 ;	--   Time +1
CONSTANT CLKSNAP_T00            =  3 ;	--   Time  0
CONSTANT CLKSNAP_TM1            =  4 ;	--   Time -1
CONSTANT CLKSNAP_TM2            =  5 ;	--   Time -2
CONSTANT CLKSNAP_TM3            =  6 ;	--   Time -3

-- The presence of all three ASR9 clocks is monitored by CLKSTS_NOCLK.
-- If this bit is set, but if CLKCNT_SIMULATE is clear, then internal
-- clocks will be forced with a delay code of zero.  This supplies
-- correctly timed fallback clocks in the event that the external
-- clocks fail during real operation.  Normal operation, using the old
-- delay value, will resume when the external clocks reappear.
-- However, when CLKCNT_SIMULATE is set, then the external clocks are
-- ignored, and the simulated clocks can be adjusted with the delay
-- selection.
 
CONSTANT RIMIO_CLKSTS         = H"05";	-- Clock Status
CONSTANT CLKSTS_NOCLK           =  0 ;	--   No ASR9 clocks right now
CONSTANT CLKSTS_NOCLK_STICKY    =  1 ;	--   Clocks were gone in the past
CONSTANT CLKSTS_013MHZ          =  5 ;	--   Status of  1.3MHz input
CONSTANT CLKSTS_026MHZ          =  6 ;	--   Status of  2.6MHz input
CONSTANT CLKSTS_103MHZ          =  7 ;	--   Status of 10.3MHz input

-- ------------------------------
-- Serial Number Management
--
-- Each PLD reports its code version number, include file version
-- number, and licensing bits using a single multiplexed port.  Two of
-- the port data bits tell which value is being reported in the other
-- 6-bits.  These two select bits are read/write, and the report bits
-- are read-only.
--
CONSTANT RIMIO_SERIAL_U1      = H"08";	-- Serial number data for U1
CONSTANT RIMIO_SERIAL_U2      = H"09";	-- Serial number data for U2
CONSTANT RIMIO_SERIAL_U3      = H"0A";	-- Serial number data for U3
CONSTANT SERIAL_REPORT0         =  0 ;	--   6-bit report field
CONSTANT SERIAL_REPORT5         =  5 ;
CONSTANT SERIAL_SELECT0         =  6 ;	--   2-bit select field
CONSTANT SERIAL_SELECT1         =  7 ;

CONSTANT SERIAL_SELECT_CODE     =  0 ;	-- Selects PLD code version */
CONSTANT SERIAL_SELECT_INCL     =  1 ;	-- Selects include file version */

-- **************************************
-- *                                    *
-- * Fully Field Programmable Functions *
-- *                                    *
-- **************************************

-- The remainder of these I/O definitions are implemented in the field
-- programmable PLDs, and thus, can be changed if necessary.

-- ------------------------------
-- Board Edge LEDs
--
-- There are four user programmable LEDs mounted at the front
-- edge of the RIM board.  Each LED's state is controlled by
-- separate SET/CLR bits, rather than by a direct load.  This
-- allows the PC to set or change one LED without having to worry
-- about preserving the others.
--
-- LEDs are allocated beginning with bit zero in each I/O byte.
--
CONSTANT RIMIO_LED_SET        = H"0C";	-- LEDs to turn on  (write only)
CONSTANT RIMIO_LED_CLR        = H"0D";	-- LEDs to turn off (write only)
CONSTANT RIMIO_LED_STATE      = H"0E";	-- LED ON states    ( read only)

-- ------------------------------
-- RAM Interface.
--
-- The memory is organized as 4Mx8.  The address for reading and
-- writing can optionally autoincrement after each access.  This
-- allows blocks of memory to be accessed efficiently.  Also, for
-- example, choosing to increment after writes but not after reads
-- would permit efficient editing of a block of memory via
-- read-modify-write.
--
-- To access the RAM, first setup the 22-bit starting address using
-- the RIMIO_MADRXX_XX ports.  Set the mode for address update using
-- RIMIO_MEMCTL, and then perform data reads and writes using
-- RIMIO_MEMDATA.
--
CONSTANT RIMIO_MADR07_00      = H"10";	-- Low address bits
CONSTANT RIMIO_MADR15_08      = H"11";	-- Middle address bits
CONSTANT RIMIO_MADR21_16      = H"12";	-- (0, 0, High address bits)

CONSTANT RIMIO_MEMCTL         = H"13";	-- Memory Access Control
CONSTANT MEMCTL_RDINC           =  0 ;	--   Autoincrement after each read
CONSTANT MEMCTL_WRINC           =  1 ;	--   Autoincrement after each write

CONSTANT RIMIO_MEMDATA        = H"14";	-- RAM memory data itself

-- ------------------------------
-- Synchronous/Asynchronous Serial Output.
--
-- The RIM can generate a serial data stream having arbitrary
-- characteristics that are completely determined by the PC.  With
-- appropriate programming, this hardware interface will support any
-- type of serial output protocol.
--
-- To accomplish this, the hardware interface merely outputs a
-- string of bits that are read from RAM; there is no particluar
-- interpretation ascribed to the sequence itself.  There are
-- eight such strings so that data buffering (no time gaps) can
-- be accomplished; and an optional idle pattern can be executed
-- whenever there is nothing else to do (See RAM Memory Map
-- below).
--
-- The data and idle strings in RAM consist of a single data bit per
-- byte, plus a STOP bit indicating the end of the string.  The data
-- bit in the STOP location will also be transmitted, i.e., it is not
-- possible to have a zero-length bit pattern.  The advantage of using
-- a STOP bit in RAM (rather than data length counters in the PLD) is
-- that there is less internal state required in the PLD.
--
-- The eight buffered data strings are output in an ascending
-- wraparound sequence using a 3-bit write pointer (WPTR) and 3-bit
-- read pointer (RPTR).  Whenever RPTR=WPTR, there is no more data to
-- output, and the IDLE string will be continually sent if the
-- SO_CSR_ENAIDLE bit is set.  To send a stream of data, first write
-- the data pattern plus stop bit to memory buffer number (WPTR+1)&7.
-- Then, write the NEWBUF bit, which will increment WPTR in a single
-- indivisible operation.  Continue writing new memory buffers and
-- setting NEWBUF, as long as (WPTR+1)&7 is not equal to RPTR.  The
-- later indicates that all buffers are presently in use.


-- The buffer pointers and status of the transmitter are given in
-- RIMIO_SO_BUFSTS, which is entirely read-only.  WPTR is incremented
-- each time the SO_CSR_NEWBUF bit is written with a "1", and RPTR
-- will be incremented after each memory buffer is fully transmitted.
-- The SO_BUFSTS_XMTDATA and SO_BUFSTS_XMTIDLE bits indicate when each
-- type of data are being transmitted.  There are also two LEDs on the
-- front of the RIM board that can indicate this same state.

CONSTANT RIMIO_SO_BUFSTS      = H"16";	-- Serial Read/Write Buffer Status
CONSTANT SO_BUFSTS_RPTR0        =  0 ;	--   3-bit Read Pointer.  Indicates
CONSTANT SO_BUFSTS_RPTR1        =  1 ;	--     the location of the next buffer
CONSTANT SO_BUFSTS_RPTR2        =  2 ;	--     to be transmitted
CONSTANT SO_BUFSTS_WPTR0        =  3 ;	--   3-bit Write Pointer.  Indicates
CONSTANT SO_BUFSTS_WPTR1        =  4 ;	--     the location of the next buffer
CONSTANT SO_BUFSTS_WPTR2        =  5 ;	--     to be filled in with data
CONSTANT SO_BUFSTS_XMTDATA      =  6 ;	--   Data bits are being sent.
CONSTANT SO_BUFSTS_XMTIDLE      =  7 ;	--   Idle bits are being sent.

-- The SO_CSR_NEWBUF and SO_CSR_RESET bits are write-only; all others
-- are read/write.  Seting SO_CSR_RESET will bring about an immediate
-- and complete reset of all SIO functions, i.e., back to their
-- initial power-up condition: the SO_CSR_ENADATA and SO_CSR_ENAIDLE
-- bits are cleared, and RPTR and WPTR are both set to zero.
--
CONSTANT RIMIO_SO_CSR         = H"17";	-- Serial Output Control/Status
CONSTANT SO_CSR_NEWBUF          =  0 ;	--   SET each time a new buffer is ready
CONSTANT SO_CSR_RESET           =  1 ;	--   Complete reset of SIO functions
CONSTANT SO_CSR_ENADATA         =  2 ;	--   Data bit streams are enabled
CONSTANT SO_CSR_ENAIDLE         =  3 ;	--   Idle bit stream is enabled
CONSTANT SO_CSR_CLKPHZ0         =  4 ;	--   Bits adjust the output clock
CONSTANT SO_CSR_CLKPHZ1         =  5 ;	--     phase within each bit time.
CONSTANT SO_CSR_DFLTOUT         =  6 ;	--   Default output level

-- The two LEDs that are normally associated with the serial
-- transmitter can also be reused as general-purpose indicators.
--
CONSTANT RIMIO_SO_LEDS        = H"18";	-- Select LED functions
CONSTANT SO_LEDS_DATA_CMD       =  0 ;	--   Data LED command (if not normal)
CONSTANT SO_LEDS_IDLE_CMD       =  1 ;	--   Idle LED command (if not normal)
CONSTANT SO_LEDS_DATA_NORM      =  2 ;	--   Data LED has normal function
CONSTANT SO_LEDS_IDLE_NORM      =  3 ;	--   Idle LED has normal function
CONSTANT SO_LEDS_DATA_STATE     =  4 ;	--   Data LED state
CONSTANT SO_LEDS_IDLE_STATE     =  5 ;	--   Idle LED state

-- Baud rate selection.  The serial output baud rate will be 153600
-- divided by one plus this value.
--
CONSTANT RIMIO_SO_BAUD        = H"19";	-- Baud rate selection

CONSTANT SO_MEMBIT_DATA         =  0 ;	-- Memory bit: data
CONSTANT SO_MEMBIT_STOP         =  1 ;	-- Memory bit: end of string
CONSTANT SO_MEMBIT_LEDON        =  2 ;	-- Memory bit: turn on LED

-- ------------------------------
-- RIM/ASR9/RVP7 Simulation Control
--
-- Various input signals from the ASR9 can be simulated locally.  This
-- allows program development to proceed, even when there is no
-- external connection to the ASR9.  Subsystems can be simulated
-- individually, so that partial simulation can be used even with a
-- real connection to an ASR9.  For example, the ACP/ARP pulses can be
-- simulated in case the antenna is not actually rotating.
--
-- The PRETO simulator is implemented as an array of desired time
-- intervals.  Likewise, the ASR9 and RVP7 (I,Q) simulators read
-- pulses of simulated data from RAM.  See the Memory Map definitions
-- below.
-- 
-- The ACP/ARP simulator produces ACP pulses at approximately 890Hz,
-- and an ARP pulse at every 4096th ACP.  The ARP therefore is
-- produced at approximatly 4.6 second intervals.
--
CONSTANT RIMIO_SIMULATE       = H"1B";	-- ASR9 Simulation Control
CONSTANT SIMULATE_PRETO         =  0 ;	--   Simulate PRETO
CONSTANT SIMULATE_ACPARP        =  1 ;	--   Simulate ACP and ARP
CONSTANT SIMULATE_ASR9IQ        =  2 ;	--   Simulate ALTC[11:0]
CONSTANT SIMULATE_RVP7IQ        =  3 ;	--   Simulate RVP7 I/Q Data

-- The simulated rate of ACP pulses is scaled by the following 8-bit
-- number as 1.3MHz / (1024 + 4*RIMIO_ACPSIM_RATE).  The rate is
-- preset to 109 on power up, giving a default ACP frequency of
-- 1.3MHz / (1024 + 4*109) = 890Hz.
--
CONSTANT RIMIO_ACPSIM_RATE    = H"1C";	-- Simulated ACP rate

-- ------------------------------
-- ASR9 Antenna Position
--
-- The ASR9 generates 4096 Antenna Control Pulse (ACP) signals per
-- revolution, and one Antenna Reset Pulse (ARP) on each North mark
-- crossing.  Antenna azimuth position is maintained as a 12-bit count
-- of ACPs within each revolution, plus a 4-bit count of ARPs that
-- have been received so far.
--
-- The antenna position is continually changing.  There is a
-- possibility that the ACP and ARP counts may change between the LO
-- and HI 8-bit reads performed by the PC.  To get around this, always
-- perform three reads (LO,HI,LO), and verify that the two LO bytes
-- are identical.  The bracketed HI byte will then be consistent with
-- the LO bits.
--
CONSTANT RIMIO_ANTPOS_LO      = H"1D";	-- ACP[7:0]
CONSTANT RIMIO_ANTPOS_HI      = H"1E";	-- ARP[3:0] ACP[11:8]

-- ------------------------------
-- STC Map Selection
--
-- Each 256K x 6-Bit STC Map is addressed by:
-- 
--      10-bit range gate counter          Bits  9.. 0
--       8-bit ACP counter                 Bits 17..10
--
-- The RIM hardware supports up to eight STC maps simultaneously
-- resident in memory.  The selection of which map is currently active
-- is made with the following three registers.  Together, they define
-- a 3-bit number that selects one of the eight maps.
--
CONSTANT RIMIO_STC_SEL0       = H"20";	-- STC Map selection bits.  These
CONSTANT RIMIO_STC_SEL1       = H"21";	--   define a 3-bit number that
CONSTANT RIMIO_STC_SEL2       = H"22";	--   selects one of eight maps.

-- One of the following values should be written to each of the above
-- ports.  These define how each STC Map selection bit is derived.
--
CONSTANT STC_SEL_ZERO           =  0 ;	-- Zero
CONSTANT STC_SEL_ONE            =  1 ;	-- One
CONSTANT STC_SEL_HIBEAM         =  2 ;	-- ASR9 HI beam selection
CONSTANT STC_SEL_CIRPOL         =  3 ;	-- ASR9 Circular polarization
CONSTANT STC_SEL_BCHAN          =  4 ;	-- ASR9 "B" channel

CONSTANT RIMIO_STC_CNT        = H"23";	-- STC Control Register
CONSTANT STC_CNT_DATPH0         =  0 ;	--   Phase selection for output data
CONSTANT STC_CNT_DATPH1         =  1 ;
CONSTANT STC_CNT_DATPH2         =  2 ;
CONSTANT STC_CNT_CLKPH0         =  3 ;	--   Phase selection for output clock
CONSTANT STC_CNT_CLKPH1         =  4 ;
CONSTANT STC_CNT_CLKPH2         =  5 ;

-- ------------------------------
-- ASR9 RF Switch Status and Control.
--
-- The present sense of all switch and status inputs can be detected
-- using the RIMIO_DGSTS mechanism.  In addition, the real input level
-- may be replaced with a simulated level that is either low or high.
--
CONSTANT RIMIO_SWSTS_SIMMASK  = H"24";	-- Mask of inputs to be simulated
CONSTANT RIMIO_SWSTS_SIMDATA  = H"25";	-- Simulated input levels

CONSTANT SWSTS_SW103            =  0 ;	--   Switch #103
CONSTANT SWSTS_SW104            =  1 ;	--   Switch #104
CONSTANT SWSTS_SW106            =  2 ;	--   Switch #106
CONSTANT SWSTS_AHI              =  3 ;	--   A channel, HI beam
CONSTANT SWSTS_BHI              =  4 ;	--   B channel, HI beam
CONSTANT SWSTS_LINPOL           =  5 ;	--   Linear polarization
CONSTANT SWSTS_CHANB            =  6 ;	--   Channel B selected
CONSTANT SWSTS_HIBIT            =  6 ;	--     (Highest bit defined)

-- Likewise, the switches that are controlled by the RIM are also read
-- back via RIMIO_DGSTS.  The switch outputs are generally under the
-- control of internal RIM algorithms, but the lines may also be
-- forced to low or high simulated levels.
--
CONSTANT RIMIO_SWCNT_SIMMASK  = H"26";	-- Mask of outputs to be simulated
CONSTANT RIMIO_SWCNT_SIMDATA  = H"27";	-- Simulated output levels

CONSTANT SWCNT_SW103            =  0 ;	--   Switch #103
CONSTANT SWCNT_SW104            =  1 ;	--   Switch #104
CONSTANT SWCNT_BEAMS            =  2 ;	--   Beam selection
CONSTANT SWCNT_HIBIT            =  2 ;	--     (Highest bit defined)

-- The switch pair 103/104 has only three well defined composite
-- states, which are interpreted as follows.
--
CONSTANT SW103104_LIN_LO        =  0 ;	-- Linear polarized, Low beam
CONSTANT SW103104_LIN_HI        =  1 ;	-- Linear polarized, High beam
CONSTANT SW103104_CIRCULAR      =  2 ;	-- Circular polarized

-- ------------------------------
-- RIN-PE Data Stream Control
--
-- These bits allow the RIN-PE interface to be started and stopped in
-- an orderly manner.  The user's start/stop request is written to the
-- read/write RINPE_CSR_RUNREQ bit, which is initially cleared on
-- powerup.  Setting RINPE_CSR_RUNREQ causes the RIN-PE data stream to
-- startup on the next radar pulse; clearing the bit causes the data
-- stream to shutdown at the end of the current pulse.  Full header
-- and data pulse sequences are guaranteed to be output in all cases
-- of starting and stopping.
--
-- The readonly RINPE_CSR_RUNSTS bit indicates that the data stream is
-- running right now.  The correct procedure for shutting down the
-- RIN-PE interface is to clear RINPE_CSR_RUNREQ, and then wait for
-- CSR_RUNSTS to also become clear.

CONSTANT RIMIO_RINPE_CSR      = H"28";	-- RIN-PE Control/Status Register
CONSTANT RINPE_CSR_RUNREQ       =  0 ;	--    Request to run the data stream
CONSTANT RINPE_CSR_RUNSTS       =  1 ;	--    Data stream is running now

-- The following variable sets the delay in (quarter-bin units)
-- between the arrival of PRETO and the generation of the SYNC word in
-- the RIN-PE output data stream.  This constant is determined by
-- experiment, using the ASR9 itself and a test target at known
-- range.
--
CONSTANT PEQBIN_SYNC            = 45 ;	-- Delay to RIN-PE SYNC word

-- ------------------------------
-- RVP7 Support Functions
--
-- HardReset: The RVP7 external reset pin will be pulsed whenever the
-- ISA bus itself is reset, or whenever a "1" is written to the
-- RVP7CSR_HARDRESET bit.  Note that the RVP7 requires approximately 2.0
-- seconds to complete its self tests after being reset.  No SCSI I/O
-- should be attempted during that time.
--
CONSTANT RIMIO_RVP7CSR        = H"29";  -- RVP7 Control/Status Register
CONSTANT RVP7CSR_HARDRESET      =  0 ;  --   Pulse the external reset line


-- ******************************************
-- *                                        *
-- * Diagnostic Input and Output Monitoring *
-- *                                        *
-- ******************************************
--
-- These I/O ports assist in the creation of semi-automated procedures
-- for checking out RIM boards and chassis in a production
-- environment.  Through these ports, all external input and output
-- lines can be directly monitored, and all output lines can be set to
-- a known state.
--
-- To economize on the allocation of port address space, the
-- diagnostic functions are handled one bit at a time through the
-- RIMIO_DGSTS and RIMIO_DGOUT locations.  This approach uses only two
-- I/O ports, rather than potentially as many as ten (which would be
-- one sixth of the total).

-- ------------------------------
-- Diagnostic Output Control
--
-- These are the external output signals that can be forced to either
-- a high or low state.  A given output is set by writing RIMIO_DGOUT
-- with the signal's select code merged with the desired state of the
-- line in DGOUT_DATA.  Only one output can be forced at a time.
--
-- When a nonzero select code is written, then the selected output
-- line will take on the indicated data level.
--
CONSTANT RIMIO_DGOUT          = H"3A";	-- Diagnostic outputs
CONSTANT DGOUT_DATA             =  7 ;	--   Output data bit is here

CONSTANT DGOUT_WP6WXTD          =  1 ;
CONSTANT DGOUT_WP6WXCK          =  2 ;
CONSTANT DGOUT_WPCX103          =  3 ;
CONSTANT DGOUT_WPCX104          =  4 ;
CONSTANT DGOUT_WPBEAMS          =  5 ;
CONSTANT DGOUT_WPSTC00          =  6 ;
CONSTANT DGOUT_WPSTC01          =  7 ;
CONSTANT DGOUT_WPSTC02          =  8 ;
CONSTANT DGOUT_WPSTC03          =  9 ;
CONSTANT DGOUT_WPSTC04          = 10 ;
CONSTANT DGOUT_WPSTC05          = 11 ;
CONSTANT DGOUT_WPSTCLK          = 12 ;
CONSTANT DGOUT_PEDAT00          = 13 ;
CONSTANT DGOUT_PEDAT01          = 14 ;
CONSTANT DGOUT_PEDAT02          = 15 ;
CONSTANT DGOUT_PEDAT03          = 16 ;
CONSTANT DGOUT_PEDAT04          = 17 ;
CONSTANT DGOUT_PEDAT05          = 18 ;
CONSTANT DGOUT_PEDAT06          = 19 ;
CONSTANT DGOUT_PEDAT07          = 20 ;
CONSTANT DGOUT_PEDAT08          = 21 ;
CONSTANT DGOUT_PEDAT09          = 22 ;
CONSTANT DGOUT_PEDAT10          = 23 ;
CONSTANT DGOUT_PEDAT11          = 24 ;
CONSTANT DGOUT_PEDAT12          = 25 ;
CONSTANT DGOUT_PEDAT13          = 26 ;
CONSTANT DGOUT_PEDAT14          = 27 ;
CONSTANT DGOUT_PEDAT15          = 28 ;
CONSTANT DGOUT_PESYNCN          = 29 ;
CONSTANT DGOUT_PEVALDN          = 30 ;
CONSTANT DGOUT_PEPHASE          = 31 ;
CONSTANT DGOUT_PERXCLK          = 32 ;
CONSTANT DGOUT_WPSPAR0          = 33 ;
CONSTANT DGOUT_WPSPAR1          = 34 ;
CONSTANT DGOUT_WPSPAR2          = 35 ;
CONSTANT DGOUT_WPSPAR3          = 36 ;

CONSTANT DGOUT_HI_LINENUM       = 36 ;	-- Highest numbered output line

-- ------------------------------
-- Diagnostic Status Monitor
--
-- Input and output signal states can be read from RIMIO_DGSTS at any
-- time; the normal operation of the RIM will not be affected.  Signal
-- levels are obtained by first writing RIMIO_DGSTS with the signal's
-- select code, followed by reading the data bit in DGSTS_DATA.
-- Either "input" or "output" line select codes may be used.
--
CONSTANT RIMIO_DGSTS          = H"3B";	-- Diagnostic status
CONSTANT DGSTS_DATA             =  7 ;	--   Returned data bit is here

CONSTANT DGIN_WPALT00           = 37 ;
CONSTANT DGIN_WPALT01           = 38 ;
CONSTANT DGIN_WPALT02           = 39 ;
CONSTANT DGIN_WPALT03           = 40 ;
CONSTANT DGIN_WPALT04           = 41 ;
CONSTANT DGIN_WPALT05           = 42 ;
CONSTANT DGIN_WPALT06           = 43 ;
CONSTANT DGIN_WPALT07           = 44 ;
CONSTANT DGIN_WPALT08           = 45 ;
CONSTANT DGIN_WPALT09           = 46 ;
CONSTANT DGIN_WPALT10           = 47 ;
CONSTANT DGIN_WPALT11           = 48 ;
CONSTANT DGIN_WPPRETO           = 49 ;
CONSTANT DGIN_WPRGATE           = 50 ;
CONSTANT DGIN_WPACP             = 51 ;
CONSTANT DGIN_WPARP             = 52 ;
CONSTANT DGIN_WPSX103           = 53 ;
CONSTANT DGIN_WPSX104           = 54 ;
CONSTANT DGIN_WPSX106           = 55 ;
CONSTANT DGIN_WPCHB             = 56 ;
CONSTANT DGIN_WPLP              = 57 ;
CONSTANT DGIN_WPAHI             = 58 ;
CONSTANT DGIN_WPBHI             = 59 ;
CONSTANT DGIN_PESPNDN           = 60 ;
CONSTANT DGIN_PENRDYN           = 61 ;
CONSTANT DGIN_WPSPAR0           = 62 ;
CONSTANT DGIN_WPSPAR1           = 63 ;
CONSTANT DGIN_WPSPAR2           = 64 ;
CONSTANT DGIN_WPSPAR3           = 65 ;

CONSTANT DGIN_HI_LINENUM        = 65 ;	-- Highest numbered input line

-- The following clock input signal monitor selections are defined in
-- the same way as all others, but they can not be used with the
-- RIMIO_DGSTS port.  These definitions are only interpreted by the
-- rim_get_line_state() API routine.
--
CONSTANT DGIN_WP013MH          = 125 ;
CONSTANT DGIN_WP026MH          = 126 ;
CONSTANT DGIN_WP103MH          = 127 ;

-- *************************************
-- *                                   *
-- * Oscilloscope Test Point Selectors *
-- *                                   *
-- *************************************

-- ------------------------------
-- There are many internal and external signals in the RIM and it
-- would be impractical to try to have test points for them all.
-- Rather, TP_COUNT scope test points are supplied, each of which has
-- a connection to both programmable PLDs (U1 and U2).  Up to TP_COUNT
-- channels of a multi-trace scope may be clipped onto these test
-- points, and the signals to view are selected in software.  You
-- never have to move the scope probes; simply hook them up once, and
-- then select what you want to view.
--
CONSTANT RIMIO_TP0            = H"3C";	-- Test point #0 selection
CONSTANT RIMIO_TP1            = H"3D";	-- Test point #1 selection
CONSTANT RIMIO_TP2            = H"3E";	-- Test point #2 selection
CONSTANT RIMIO_TP3            = H"3F";	-- Test point #3 selection

CONSTANT TP_COUNT               = 2 ;	-- Number of test points

-- ------------------------------
-- The following signals are sourced by U1.  All of these codes must
-- have the 80H bit clear.
--
CONSTANT TPU1_WP103MHD        = H"01";	-- 10.3MHz ASR9 clock
CONSTANT TPU1_WP026MHD        = H"02";	--  2.6MHz ASR9 clock
CONSTANT TPU1_WP013MHD        = H"03";	--  1.3MHz ASR9 clock
CONSTANT TPU1_PCBCLK          = H"04";	-- ISA bus system clock

CONSTANT TPU1_WPALT00         = H"05";	-- ASR9 I/Q data bit 0
CONSTANT TPU1_WPALT11         = H"06";	-- ASR9 I/Q data bit 11

CONSTANT TPU1_IBDCLK          = H"07";	-- RVP7 I/Q clock
CONSTANT TPU1_IBDCLR          = H"08";	-- RVP7 I/Q reset
CONSTANT TPU1_IBD00           = H"09";	-- RVP7 I/Q data bit 0
CONSTANT TPU1_IBD15           = H"0A";	-- RVP7 I/Q data bit 15
CONSTANT TPU1_IBD16           = H"0B";	-- RVP7 I/Q data bit 16
CONSTANT TPU1_IBD17           = H"0C";	-- RVP7 I/Q data bit 17

CONSTANT TPU1_TGEN4           = H"0D";	-- RVP7 Trigger generator #4
CONSTANT TPU1_TGEN5           = H"0E";	-- RVP7 Trigger generator #5
CONSTANT TPU1_INTRIG          = H"0F";	-- RVP7 Trigger source

CONSTANT TPU1_PESPNDN         = H"10";	-- RIN-PE suspend
CONSTANT TPU1_PENRDYN         = H"11";	-- RIN-PE not-ready
CONSTANT TPU1_PERXCLK         = H"12";	-- RIN-PE data clock
CONSTANT TPU1_PEPHASE         = H"13";	-- RIN-PE data phase
CONSTANT TPU1_PESYNCN         = H"14";	-- RIN-PE sync
CONSTANT TPU1_PEVALDN         = H"15";	-- RIN-PE valid
CONSTANT TPU1_PEDAT00         = H"16";	-- RIN-PE data bit 0
CONSTANT TPU1_PEDAT15         = H"17";	-- RIN-PE data bit 15

CONSTANT TPU1_IQSAMP0         = H"18";	-- Sampling points #1 and #2 for ASR9
CONSTANT TPU1_IQSAMP1         = H"19";	--  (rising) and RVP7 (falling) data.

CONSTANT TPU1_WPACP           = H"1A";	-- ASR9 antenna control pulse
CONSTANT TPU1_WPARP           = H"1B";	-- ASR9 antenna reset pulse
CONSTANT TPU1_AZ0000          = H"1C";	-- Low four bits of AZ are zero

CONSTANT TPU1_HIBEAM          = H"1D";	-- HI beam indicator, delayed

-- ------------------------------
-- The following signals are sourced by U2.  All of these codes must
-- have the 80H bit set.
--
CONSTANT TPU2_013MID          = H"81";	-- Mid point of 1.3MHz data
CONSTANT TPU2_013END          = H"82";	-- End point of 1.3MHz data

CONSTANT TPU2_WP6WXCLK        = H"83";	-- ASR9 serial clock
CONSTANT TPU2_WP6WXTD         = H"84";	-- ASR9 serial transmit data

CONSTANT TPU2_WPSTCLK         = H"85";	-- ASR9 STC clock
CONSTANT TPU2_WPSTC00         = H"86";	-- ASR9 STC data bit 0
CONSTANT TPU2_WPSTC05         = H"87";	-- ASR9 STC data bit 5

CONSTANT TPU2_WPGATEO         = H"88";	-- ASR9 range gate
CONSTANT TPU2_WPPRETO         = H"89";	-- ASR9 pretrigger
CONSTANT TPU2_WPAHI           = H"8A";	-- ASR9 "A" Hi beam
CONSTANT TPU2_WPBHI           = H"8B";	-- ASR9 "B" Hi beam
CONSTANT TPU2_WPLP            = H"8C";	-- ASR9 linear polarization
CONSTANT TPU2_WPCHB           = H"8D";	-- ASR9 Chan "B"

CONSTANT TPU2_WPCX103         = H"8E";	-- ASR9 switch 103 control
CONSTANT TPU2_WPSX103         = H"8F";	-- ASR9 switch 103 sense
CONSTANT TPU2_WPCX104         = H"90";	-- ASR9 switch 104 control
CONSTANT TPU2_WPSX104         = H"91";	-- ASR9 switch 104 sense
CONSTANT TPU2_WPSX106         = H"92";	-- ASR9 switch 106 sense
CONSTANT TPU2_WPBEAMS         = H"93";	-- ASR9 beam select

-- *****************************
-- *                           *
-- * Static I/O RAM Memory Map *
-- *                           *
-- *****************************

CONSTANT RIMEM_SIZE         = H"400000";  -- RAM Size (4-MBytes)

-- ------------------------------
-- STC Map definitions

CONSTANT RIMEM_STCMAP_BASE  = H"000000";  -- STC Map base address

CONSTANT RIMEM_STCMAP_SECTORS  =   256 ;  -- 256 sectors per 360 degrees
CONSTANT RIMEM_STCMAP_SECTSIZE =  1024 ;  -- 1024 range cells (1.3 MHz clocks)
CONSTANT RIMEM_STCMAP_SIZE = (RIMEM_STCMAP_SECTORS * RIMEM_STCMAP_SECTSIZE) ;

CONSTANT RIMEM_STCMAP_NUM     =      8 ;  -- Number of STC Maps

-- ------------------------------
-- Allocations for serial bitstream output.  RIMEM_SO_SIZE is the
-- maximum length (in bits) of the Data-Plus-STOP portion of any
-- single transmission.

CONSTANT RIMEM_SO_SIZE_BITS   = 10 ;
CONSTANT RIMEM_SO_SIZE        = (2 ^ RIMEM_SO_SIZE_BITS) ;

CONSTANT RIMEM_SO_DATABUF0  = H"200000";  -- Data Buffer #0 address
CONSTANT RIMEM_SO_IDLEBUF   = H"202000";  -- Idle Buffer

-- ------------------------------
-- The internal simulator for PRETO (ASR9 Pretrigger) uses an array of
-- desired time intervals between successive PRETO pulses.  These time
-- intervals are measured as 14-bit counts of the 1.3MHz clock.  The
-- counts reside in the lower fourteen bits of a 16-bit word, which is
-- then stored at pairs of memory bytes; the low byte of each 16-bit
-- value occupying the lower address of the pair.
--
CONSTANT RIMEM_PRETO_SIMTAB = H"204000";  -- Base of simulated trigger times

-- The end of the sequence of time intervals is controlled by a 2-bit
-- code in the upper bits of each 16-bit word.  The ending condition
-- may be forced, or it may depend on the state of other signals
-- within the RIM.  This allows PRETO to sync up with other logic.  In
-- all cases, the ending condition applies AFTER the completion of the
-- simulated period contained in the low part of the 16-bit word.
--
-- A maximum of 64 successive time intervals can be specified.  If no
-- explicit end is found in the first 64 slots, the simulator will
-- wrap around to the beginning of the table anyway.
--
CONSTANT PRETO_CODE_CONTINUE  =      0 ;  -- Normal continuation
CONSTANT PRETO_CODE_END       =      1 ;  -- End of list
CONSTANT PRETO_CODE_ACP16X    =      2 ;  -- End if the antenna angle has passed
                                          --   through a multiple of 16.
-- ------------------------------
-- The internal simulator for ASR9 and RVP7 (I,Q) read preloaded 8-bit
-- values into the most significant bits of each data sample.
--
CONSTANT RIMEM_ASR9_SIMIQ   = H"205000";  -- Base of 2048 pairs of simulated
CONSTANT RIMEM_RVP7_SIMIQ   = H"206000";  --   (I,Q) data bytes
