/* **********************************************************************
 * *                                                                    *
 * *     RDA System Ethernet Board-Level Driver Library Definitions     *
 * *                                                                    *
 * **********************************************************************
 * File: include/netcards_lib.h
 *
 *                        COPYRIGHT (c) 2006  BY
 *              VAISALA INC., WESTFORD MASSACHUSETTS, U.S.A.
 * 
 * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND  COPIED
 * ONLY  IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE
 * INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE  OR  ANY OTHER
 * COPIES  THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY
 * OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE  IS  HEREBY
 * TRANSFERED.
 */
#ifndef SIGMET_NETCARDS_LIB_H
#define SIGMET_NETCARDS_LIB_H 1

/* *******************************
 * *                             *
 * * Message Catalog Definitions *
 * *                             *
 * *******************************
 */
#define      NOCLKPARAMS         1
#define NETC_NOCLKPARAMS        (NETCARDS_FACILITY + NOCLKPARAMS)

#ifndef MESSAGE_ONLY

/* **************************
 * *                        *
 * *  RVP9/IFD Definitions  *
 * *                        *
 * **************************
 */

/* ========================================
 * ============= ifdclocks.c ==============
 * ========================================
 */
/* The IFD sample clock is derived from the VCO using a PLL in which
 * one of the feedback loops contains a DDS.
 */
struct ifdClockParams {
  FLT8  fRefMHz ;		/* Input reference frequency */
  FLT8  fOutMHz ;		/* Sampling clock output frequency */
  FLT8  fVcoMHz ;		/* Internal VCO operating frequency */
  FLT8  fDdsMHz ;		/* DDS chip clock frequency */
  FLT8  fSinMHz ;		/* DDS synthesized sinewave frequency */
  FLT8  fPfdMHz ;		/* PLL Phase-Freq-Detector frequency */
  SINT4 iPreScl ;		/* VCO prescaler */
  SINT4 iDivVcoToOut ;		/* Divider for VCO -> Output clock */
  SINT4 iDivVcoToDds ;		/* Divider for VCO -> DDS clock */
  SINT4 iDivSinToPfd ;		/* Divider for Sinewave  -> PFD phase detector */
  SINT4 iDivRefToPfd ;		/* Divider for Reference -> PFD phase detector */
  SINT4 nVariations ;		/* Number of feasible solutions */
  FLT4  fScore ;		/* Quality score (harmonics and spurs) */
} ;

MESSAGE rvp9ifdClockParams
( FLT8 fRefMHz_a, FLT8 fOutMHz_a, struct ifdClockParams *cp_a,
  FILE * pDiagStream_a ) ;

void printIfdClockParams
( FILE *pStream_a, const struct ifdClockParams *cp_a ) ;

#endif /* #ifndef MESSAGE_ONLY */
#endif /* #ifndef SIGMET_NETCARDS_LIB_H */
