/**C*
 *
 * Vaisala software source code file
 *
 * Copyright (c) Vaisala Oyj 2007, 2011, 2012, 2013.
 * All rights reserved.
 *
 **C*/

/** @file
 *
 * Shared Component Definitions Specific to Weather Radar
 *
 * $URL: https://subversion.vaisala.com/svn/repos/sigmet/wr_iris_rda/tags/release8.13.6/base/include/embhw/wr_modules.h $
 *
 * $Id: wr_modules.h 30247 2014-09-23 15:37:04Z rke $
 *
 */

#ifndef EMB_WR_MODULES_H
#define EMB_WR_MODULES_H 1

/* Input A/D selection bits for streaming output as well as live
 * buffered sampling.
 */
#define WRIFX_ADC_CH1  0        /* Select A/D IF-1 through IF-4 */
#define WRIFX_ADC_CH2  1
#define WRIFX_ADC_CH3  2
#define WRIFX_ADC_CH4  3
#define WRIFX_ADC_TXB  4        /* Select A/D Tx Burst */
#define WRIFX_ADC_SIM  5        /* Select burst midpoint simulation */
#define WRIFX_ADC_WD0  6        /* Select wide dynamic range sample */
#define WRIFX_ADC_WD1  7

/* Status bit results from wrifx_statusMonitorADC()
 */
#define WRIFX_MONI_DONE  0x0001 /* Done storing A/D sample data */
#define WRIFX_MONI_ERROR 0x0002 /* FIFO overflow during A/D recording */
#define WRIFX_DEVICE_ERROR 0x0004 /* mux is not in design */
#define WRIFX_PARAM_ERROR 0x0008 /* parameter is incorrect */
#define WRIFX_DIDNOT_RUN 0x00010 /* data collection did not start */

/* Burst pulse selection options for wrcvr_start()
 */
#define WRCVR_BSEL_TXB   0      /* Normal IF-Burst A/D input */
#define WRCVR_BSEL_SIM   1      /* Midpoint burst sample simulation */
#define WRCVR_BSEL_RXD   2      /* Same Rx channel as used elsewhere */

/* Each entry in the formatted history table describes a single pulse of
 * data as a structure having the following format.
 */
struct wrfmt_rawHist {          /* Single entry in the 'history' table */
  struct wrfmt_rawData *pData ; /* Avalon address of this pulse's data */
  UINT4 iHdrInternal ;          /* Internal information from formatter itself */
  UINT4 iHdrA, iHdrB, iHdrC, iHdrD ; /* Four 32-bit externally supplied words */
} ;
#define WRFMT_HISTWRAP( iHdrInternal ) (((iHdrInternal)     ) & WRFMT_WRAPMASK)
#define WRFMT_DATAWRAP( iHdrInternal ) (((iHdrInternal) >> 4) & WRFMT_WRAPMASK)
#define WRFMT_WRAPMASK 0xF

/* Likewise, each 32-bit data word consists of an (I,Q) pair packed as
 * follows.
 */
struct wrfmt_rawData {          /* Single entry in the 'data' table */
  UINT2 iPackI, iPackQ ;        /* Packed (I,Q) pair */
} ;

/* Macros to extract information from raw pulse history structures that
 * were recorded by a WR_FMT_IQ module driven by the downconversion HDL
 * module.  Must be careful here not to read stale versions out of the
 * NIOS data cache.
 */
#define WRCVR_HIST_UNCACHED( pHist ) ((struct wrfmt_rawHist *)AVALON_UNCACHED(pHist))
#define WRCVR_HIST_PDATA( pHist )        ( WRCVR_HIST_UNCACHED(pHist)->pData )
#define WRCVR_HIST_IHDRINTERNAL( pHist ) ( WRCVR_HIST_UNCACHED(pHist)->iHdrInternal )
#define WRCVR_HIST_ADCTIM( pHist )       ( WRCVR_HIST_UNCACHED(pHist)->iHdrA )
#define WRCVR_HIST_PBITS( pHist )        ( WRCVR_HIST_UNCACHED(pHist)->iHdrB )
#define WRCVR_HIST_MISC( pHist )         ( WRCVR_HIST_UNCACHED(pHist)->iHdrC )
#define WRCVR_HIST_UTAGS( pHist )        ( WRCVR_HIST_UNCACHED(pHist)->iHdrD )

#define WRCVR_MISC_TGBANK( iMisc )  (  (iMisc) & 0xFF )
#define WRCVR_MISC_FBANK( iMisc )   (( (iMisc) & 0x00000100 ) != 0)
#define WRCVR_MISC_LBANK( iMisc )   (( (iMisc) & 0x00000200 ) != 0)
#define WRCVR_MISC_FSEQ( iMisc )    (( (iMisc) & 0x00000400 ) != 0)
#define WRCVR_MISC_LSEQ( iMisc )    (( (iMisc) & 0x00000800 ) != 0)
#define WRCVR_MISC_BLANKED( iMisc ) (( (iMisc) & 0x00001000 ) != 0)

/* Timeseries GetPulse routines use the following structure and common
 * exit codes.
 */
#define WRDNC_MAX_CHANS 2       /* Max parallel downconvert channels */

struct wrcvrPulseSet {
  UINT4 iAdcTime ;              /* A/D absolute time of this pulse */
  UINT4 iPrevPRT, iNextPRT ;    /* Time increments from last / to next */
  UINT4 iPBits ;                /* Pulse bits from trigger generator */
  UINT4 iMisc ;                 /* Other bits extracted via WRCVR_MISC_XXX */
  UINT4 iUTags ;                /* Pulse tag bits supplied externally by user */
  SINT4 iTotalWordsData ;       /* Total length of all pulse data */
  struct wrcvrPulseChan {       /* The N-Channels of information */
    const struct wrfmt_rawHist *pHist ;    /* ==> Raw history header */
    const struct wrfmt_rawData *pData[2] ; /* ==> 1st and 2nd runs of data */
    SINT4                  nWordsData[2] ; /* Length of 1st and 2nd runs of data */
    UINT4 iHdrInternal ;                   /* WR_FMT_IQ internal info for wraps */
  } chans[ WRDNC_MAX_CHANS ] ;
} ;
#define WRCVR_TSX_SUCCESS   0   /* Successful exit, pulse set found */
#define WRCVR_TSX_STOPPED   1   /* Receiver is stopped, no data can be returned */
#define WRCVR_TSX_NOTAVAIL  2   /* The desired data are not (yet) available */
#define WRCVR_TSX_ERRSYNC   3   /* Internal error - Can't sync multiple channels */
#define WRCVR_TSX_ERROVHDR  4   /* Internal error - Old header was overwritten */
#define WRCVR_TSX_ERROVDAT  5   /* Internal error - Old data were overwritten */

/* Diagnostics to exercise the Weather Radar (I,Q) Data Formatter on the
 * assumption that Nios can write the input data port.
 */
struct wrfmt_diagArgs {
  struct wrfmt_rawHist *pHist ; /* Externally allocated history */
  struct wrfmt_rawData *pData ; /*   and data table arrays. */
  SINT4 iHistSize, iDataSize ;  /* Sizes (dimensions, not byte size) */
  UINT4 iHdrA, iHdrB, iHdrC, iHdrD ; /* Four 32-bit externally supplied words */
} ;
#define WRFMT_DG_RESETZER   0x00000001 /* Prog reset leaves registers zeroed */
#define WRFMT_DG_RBHISTLO   0x00000002 /* Readback history table low addr */
#define WRFMT_DG_RBHISTHI   0x00000004 /* Readback history table high addr */
#define WRFMT_DG_RBHISTPTR  0x00000008 /* Readback history table write ptr */
#define WRFMT_DG_RBDATALO   0x00000010 /* Readback data table low addr */
#define WRFMT_DG_RBDATAHI   0x00000020 /* Readback data table high addr */
#define WRFMT_DG_RBDATAPTR  0x00000040 /* Readback data table write ptr */
#define WRFMT_DG_DATACNT    0x00000080 /* Data pointer table limit wrap */
#define WRFMT_DG_DATAVAL    0x00000100 /* Incorrect data logged */
#define WRFMT_DG_DATAWRAP   0x00000200 /* NOWRAP failed on data wraparound */
#define WRFMT_DG_HISTCMP    0x00000400 /* History table written incorrectly */

/* ------------------------------
 * Static configuration of Digital I/O on the RVP9/IFD
 */
struct rvp9IFDIO_u4 {
  SINT4 select ;                /* Toplevel I/O system, IOSYS_SEL_xxx */
#define IFDIOSEL_NONE     0     /*   No subsystem presently defined */
#define IFDIOSEL_COMMON   1     /*   Use COMMON I/O subsystem */
#define IFDIOSEL_TDWR     2     /*   Use TDWR I/O subsystem */
#define IFDIOSEL_WSR98D   3     /*   Use WSR98D I/O subsystem */
#define IFDIOSEL_ORDA88D  4     /*   Use ORDA88D I/O subsystem */
#define IFDIOSEL_NCODES    5

  /* ---------- "COMMON" I/O SubSystem Definitions ----------
   */
  UINT4 comDiroutTTL ;          /* Line direction assignments */
  UINT4 comDiroutDiff ;
  UINT4 comDiroutTrig ;

  /* The Common I/O model permits connecting any of the following pins
   * with "live" capability (able to carry a fast/live signal such as a
   * trigger) to a variety of internal logical signal functions.
   */
  SINT4 comLiveTTLs [ 20 ] ;    /* Live TTL signals */
  SINT4 comLiveDiffs[ 20 ] ;    /* Live RS-422 signals */
  SINT4 comLiveTrigs[  2 ] ;    /* Live Trigger/SMA signals */

  /* -------- Available Live I/O Signals -------- */
#define COMM_LSIG_NONE          -1  /* No signal (use programed I/O) */
#define COMM_LSIG_EMPTY          0  /* Grounded output, unused input */

#define COMM_LSIG_TRIG0          1  /* User trigger outputs */
#define COMM_LSIG_TRIG1          2 
#define COMM_LSIG_TRIG2          3 
#define COMM_LSIG_TRIG3          4 
#define COMM_LSIG_TRIG4          5 
#define COMM_LSIG_TRIG5          6 
#define COMM_LSIG_TRIG6          7 
#define COMM_LSIG_TRIG7          8 
#define COMM_LSIG_TRIG8          9 
#define COMM_LSIG_TRIG9         10 
#define COMM_LSIG_TXPH0         11  /* Tx phase modulation */
#define COMM_LSIG_TXPH1         12 
#define COMM_LSIG_TXPH2         13 
#define COMM_LSIG_TXPH3         14 
#define COMM_LSIG_TXPH4         15 
#define COMM_LSIG_TXPH5         16 
#define COMM_LSIG_TXPH6         17 
#define COMM_LSIG_TXPH7         18 
#define COMM_LSIG_POLAR0        19  /* Tx polarization */
#define COMM_LSIG_POLAR1        20
#define COMM_LSIG_DAFC          21  /* DAFC serial stream */
#define COMM_LSIG_SIO0          22  /* Programmable serial data stream */
#define COMM_LSIG_BLANKED       23  /* Triggers are blanked now */
#define COMM_LSIG_UTGSIMCLK     24  /* User TAGs simulator CLOCK */
#define COMM_LSIG_UTGSIMDAT     25  /* User TAGs simulator DATA */
#define COMM_LSIG_UTGSIMENA     26  /* User TAGs simulator ENABLE */

#define COMM_LSIG_EXTRIG        27  /* External trigger input */
#define COMM_LSIG_BLANKREQ      28  /* Request to blank triggers */
#define COMM_LSIG_UTGEXTCLK     29  /* User TAGs external input CLOCK */
#define COMM_LSIG_UTGEXTDAT     30  /* User TAGs external input DATA */
#define COMM_LSIG_UTGEXTENA     31  /* User TAGs external input ENABLE */

#define COMM_LSIG_INVERTSIG      8  /* Bit to invert a live signal */
} ;

/* LED control on custom TDWR panel
 */
#define STRUCT_TDWRSETLEDS_U4_DEFINED 1
struct tdwrSetLEDs_u4 {
  SINT4 ledRFGFLT  ;            /* RF-Generator Fault LED */
  SINT4 ledSTABFLT ;            /* Stability Fault LED */
  SINT4 ledARP     ;            /* Antenna Reset Pulse LED */
  SINT4 ledACP     ;            /* Antenna Change Pulse LED */
  SINT4 ledCALTST  ;            /* Calibrate/Test Mode LED */
  SINT4 led18V     ;            /* REX +18V power okay LED */
  SINT4 led5V      ;            /* REX +5V power okay LED */
  SINT4 ledRVP9    ;            /* Linux/RVP9 GO status LED */
  SINT4 ledTDWR    ;            /* Linux/TDWR GO status LED */
} ;
#define TDWR_LED_NOCHANGE  0    /* Make no change to LED */
#define TDWR_LED_FORCEON   1    /* Force the LED 'ON' */
#define TDWR_LED_FORCEOFF  2    /* Force the LED 'OFF' */
#define TDWR_LED_OPERATE   3    /* LED follows driver hardware */

/* TDWR output lines under program control, and input status lines.
 */
struct tdwrSetIO_u4 {
  SINT4 ioRFSW ;                /* RF UpConverter Switch */
  SINT4 ioRFTST ;               /* RF Test Switch */
  SINT4 ioRFTSTPP ;             /* RF Pilot Pulse Switch */
  SINT4 ioRFTSTTER ;            /* RF Test Term Switch */
  SINT4 ioCABLEID ;             /* Cable correctness probe */
  SINT4 ioXMTSTABEN ;           /* Enable Stability Monitor */
#define TDWR_SETIO_NOCHANGE   0 /*   Make no change to output line */
#define TDWR_SETIO_SET        1 /*   Set the output line (1) */
#define TDWR_SETIO_CLR        2 /*   Clear the output line (0) */
} ;

#define STRUCT_TDWRGETIO_U4_DEFINED 1
struct tdwrGetIO_u4 {
  SINT4 iPIO ;
#define TDWR_PIO_RFSW         0 /* RF UpConverter Switch */
#define TDWR_PIO_RFTST        1 /* RF Test Switch */
#define TDWR_PIO_RFTSTPP      2 /* RF Pilot Pulse Switch */
#define TDWR_PIO_RFTSTTER     3 /* RF Test Term Switch */
#define TDWR_PIO_CABLEID_TX   4 /* Cable correctness probe (Out) */
#define TDWR_PIO_XMTSTABEN    5 /* Enable Stability Monitor */

#define TDWR_PIO_TRLFLT       8 /* TRL Fault */
#define TDWR_PIO_STABFLT1     9 /* Stability Monitor Fault #1 */
#define TDWR_PIO_STABFLT2    10 /* Stability Monitor Fault #2 */
#define TDWR_PIO_STABBSY     11 /* Stability Monitor Busy */
#define TDWR_PIO_ARP         12 /* Antenna Reset Pulse */
#define TDWR_PIO_ACP         13 /* Antenna Control Pulse */
#define TDWR_PIO_STCFLT      14 /* STC Fault */
#define TDWR_PIO_RFXTALFM    15 /* Crystal Fault */
#define TDWR_PIO_MULTRF      16 /* Multiplier Fault */
#define TDWR_PIO_RFFM        17 /* RF Generator Fault */
#define TDWR_PIO_RFLOFM      18 /* RF LO Generator Fault */
#define TDWR_PIO_RFTSTFM     19 /* RF Test Fault */
#define TDWR_PIO_CABLEID_RX  20 /* Cable correctness probe (In) */

#define TDWR_PIO_SAMP5UP     27 /* STCFLT   sampled by Trig[5] rise */
#define TDWR_PIO_SAMP5DN     28 /* STABFLT2 sampled by Trig[5] fall */
#define TDWR_PIO_SAMP6UP     29 /* RFFM     sampled by Trig[6] rise */
#define TDWR_PIO_SAMP6DN     30 /* STABFLT1 sampled by Trig[6] fall */
#define TDWR_PIO_SAMP7UP     31 /* TRLFLT   sampled by Trig[7] rise */

  FLT4 fRex5VA, fRex18VA ;      /* Measured voltages from REX */
  FLT4 fRex5VB, fRex18VB ;      /*   power line panel monitor. */
} ;

/* Available TDWR triger testpoint signals to monitor
 */
#define TDWR_TRG_RFAMPGT      0 /*   Output: DIFF[ 0] */
#define TDWR_TRG_BPIGT        1 /*   Output: DIFF[ 1] */
#define TDWR_TRG_PFNGT        2 /*   Output: DIFF[ 2] */
#define TDWR_TRG_STCTRG       3 /*   Output: DIFF[ 3] */
#define TDWR_TRG_STCCLK       4 /*   Output: DIFF[ 4] */
#define TDWR_TRG_STCBDCLK     5 /*   Output: DIFF[ 5] */
#define TDWR_TRG_STCDATA      6 /*   Output: DIFF[ 6] */
#define TDWR_TRG_PANCLK       7 /*   Output: DIFF[ 7] */
#define TDWR_TRG_TRLFLT       8 /*   Input:  DIFF[10] */
#define TDWR_TRG_STABFLT1     9 /*   Input:  DIFF[11] */
#define TDWR_TRG_STABFLT2    10 /*   Input:  DIFF[12] */
#define TDWR_TRG_STABBSY     11 /*   Input:  DIFF[13] */
#define TDWR_TRG_ARP         12 /*   Input:  DIFF[14] */
#define TDWR_TRG_ACP         13 /*   Input:  DIFF[15] */
#define TDWR_TRG_STCFLT      14 /*   Input:  DIFF[16] */
#define TDWR_TRG_XMTSTABEN   15 /*   Output: DIFF[18] */

#define TDWR_TRG_RFSW        16 /*   Output:  TTL[ 0] */
#define TDWR_TRG_RFTST       17 /*   Output:  TTL[ 1] */
#define TDWR_TRG_RFTSTPP     18 /*   Output:  TTL[ 2] */
#define TDWR_TRG_RFTSTTER    19 /*   Output:  TTL[ 3] */
#define TDWR_TRG_RFXTALFM    20 /*   Input:   TTL[10] */
#define TDWR_TRG_MULTRF      21 /*   Input:   TTL[11] */
#define TDWR_TRG_RFFM        22 /*   Input:   TTL[12] */
#define TDWR_TRG_RFLOFM      23 /*   Input:   TTL[13] */
#define TDWR_TRG_RFTSTFM     24 /*   Input:   TTL[14] */

#define TDWR_TRG_RVPTRIG_08  30 /*   RVP9 Trigger #8 (origin-0) */
#define TDWR_TRG_RVPTRIG_09  31 /*   RVP9 Trigger #9 (origin-0) */

/* Available TDWR STC modes
 */
#define TDWR_STC_NORMAL       0 /* Normal running mode */
#define TDWR_STC_MINIMUM      1 /* Remain at minimum attenuation */
#define TDWR_STC_MAXIMUM      2 /* Remain at maximum attenuation */
#define TDWR_STC_LOAD         3 /* Load new serial table data */


#define STRUCT_WSR98DSETIO_U4_DEFINED 1
struct wsr98dSetIO_u4 {
  /* Control bits set in softplane.conf */
  /* J3 Tx Trigger Control Bits */
  UINT4 iShortBeamPulseSel; 
  UINT4 iShortRfPulseSel;   
  /* J8 Rf Test Selection Bits */
  UINT4 iDrSigPos1;         
  UINT4 iDrSigPos2;          
  UINT4 iDrSigPos3;          
  UINT4 iDrSigPos4; 
  /* J9 Attenuator Control Bits */
  UINT4 iDriveSig1dB;
  UINT4 iDriveSig2dB;
  UINT4 iDriveSig4dB;
  UINT4 iDriveSig8dB;
  UINT4 iDriveSig16dB;
  UINT4 iDriveSig32dB;
  UINT4 iDriveSig40dB;
  /* J10 Noise Source Control Bits */
  UINT4 iNoiseCtrlin;
  UINT4 iP5Ion;
  /* J11 RF Test Switch Control Bits */
  UINT4 iDrSigBit1;
  UINT4 iDrSigBit2;
  UINT4 iDrSigBit3;
  UINT4 iDrSigBit4;
  /* RCP Test Point Control and Value bits */
  UINT4 iEnaRcpTp1;  /* J22 TP-1 Enable bit */
  UINT4 iEnaRcpTp2;  /* J23 TP-2 Enable bit */
  UINT4 iValRcpTp1;  /* J22 TP-1 Output */
  UINT4 iValRcpTp2;  /* J23 TP-2 Output */
  /* Software controled LED */
  UINT4 iLedDauOk;     /* DAU Serial Port Status LED */
  UINT4 iLedDcuOk;     /* DCU Serial Port Status LED */
  UINT4 iLedRvpGo;     /* RVP GO Status bit to control GO led */
  UINT4 iLedRcpGo;     /* RCP GO Status bit to control GO led */
  /* Spare Signal going to CPLD on Panel */
  UINT4 iSpare;       
  /* State Control bits for trigger control */
  UINT4 iRadReq;    
  UINT4 iRfdSeqReq;
  UINT4 iCwTestReq;
  UINT4 iRxProtReq;
  /* J7 RF Generator */
  UINT4 iPhCohoSelForce;
  UINT4 iPhCohoSelLevel;
  /* Spare control bits */
  UINT4 iSpareCtrlBit1;
  UINT4 iSpareCtrlBit2;
  /* Control bits set in RVP */
  UINT4 iPulseRateInt0;
  UINT4 iPulseRateInt1;
  UINT4 iPulseRateInt2;
  /* Control bits set in DSPX */
  UINT4 iValRvpTp1;
  UINT4 iValRvpTp2;
  /* Engineering Debug */
  UINT4 iForceUpdate;
  /* ADC Control */
  UINT4 iAdcChannelNum; /* Selects which input to sample */
  UINT4 iAdcTriggerNum; /* Selects which trigger number to use */
  UINT4 iAdcSampleRate; /* Enter sample rate in number of usec */
  UINT4 iAdcSampleNum;  /* Number of trigger results to average */
  /* Extra expansion bits to 64 words */
  UINT4 iPad46x18[18];
};

#define WSR98D_SETIO_MSK      0x80000000 /*   Make no change if bit is clear */
#define WSR98D_SERIAL_BAUD    0x8
#define STRUCT_WSR98DGETIO_U4_DEFINED 1
struct wsr98dGetIO_u4 {
  /* Input status from pins */
  UINT4 iChanFail;
  UINT4 iCohoRefFail;
  UINT4 iPhModFail;
  UINT4 iOpFreqRefFl;
  /* radiation state status */
  UINT4 iRadiate;
  UINT4 iRfdTest;
  UINT4 iCwTest;
  UINT4 iRxProtOk;
  /* currently unused bits */
  UINT4 iSpareStatBit1;
  UINT4 iSpareStatBit2;
  /* Version of the Panel */
  UINT4 iPanelVersion; 
  /* What IO mode the IFDR is in */
  UINT4 iIfdrIoMode;
  /* ADC outputs */
  SINT4 iAdcAvg; /* Average ADC value in mV */
  UINT4 iAdcSamplesNum; /* Number of samples taken */
  /* Extra expansion bits to 32 words */
  UINT4 iPad14x18[18];
};

  // RVP Testpoint MUX decode values
#define WSR98D_RVPTP_NONE          0  
#define WSR98D_RVPTP_RFGATE        1  
#define WSR98D_RVPTP_PULSE_START   2 
#define WSR98D_RVPTP_RF_DRIVE      3 
#define WSR98D_RVPTP_FILA_RESET    4 
#define WSR98D_RVPTP_POST_CHARGE   5 
#define WSR98D_RVPTP_MOD_CHARGE    6 
#define WSR98D_RVPTP_MOD_DISCHARGE 7
#define WSR98D_RVPTP_TRIG_CHARGE   8 
#define WSR98D_RVPTP_PROTECT_CMD   9
#define WSR98D_RVPTP_PROTECT_RSP   10 
#define WSR98D_RVPTP_UPDATE_IN     11 
#define WSR98D_RVPTP_UP_TIME1      12 
#define WSR98D_RVPTP_PHCOHOSEL     13 
#define WSR98D_RVPTP_UP_CLK        14 
#define WSR98D_RVPTP_UP_DATA       15 
#define WSR98D_RVPTP_UP_SEL        16 
#define WSR98D_RVPTP_MAX           16
// WSR98D Diagnostic Force bits
#define WSR98D_FORCE_ENA        0
#define WSR98D_FORCE_TRIGFORCE  2
#define WSR98D_FORCE_PHASEFORCE 3
#define WSR98D_FORCE_LEDFORCE   4
#define WSR98D_FORCE_PHASE_BLO  8
#define WSR98D_FORCE_PHASE_BHI  14
#define WSR98D_FORCE_TRIG_BLO   15
#define WSR98D_FORCE_TRIG_BHI   24
#define WSR98D_FORCE_RFGATE     15
#define WSR98D_FORCE_RFPULSE    16
#define WSR98D_FORCE_RFDRIVE    17
#define WSR98D_FORCE_FILARESET  18
#define WSR98D_FORCE_POSTCHRG   19
#define WSR98D_FORCE_MODCHRG    20
#define WSR98D_FORCE_MODDISCHRG 21
#define WSR98D_FORCE_TRIGCHRG   22
#define WSR98D_FORCE_PROTCMD    23
#define WSR98D_FORCE_RVPTIME1   24
#define WSR98D_FORCE_GOLED      25

#define STRUCT_ORDA88DSETIO_U4_DEFINED 1
struct orda88dSetIO_u4 {
  /* Control bits set in softplane.conf */
  /* J1 Tx Trigger Control Bits */
  UINT4 iShortBeamPulseSel; 
  UINT4 iShortRfPulseSel;   
  /* Spare Signal going to CPLD on Panel */
  UINT4 iSpare;       
  /* Spare control bits */
  UINT4 iSpareCtrlBit1;
  UINT4 iSpareCtrlBit2;
  /* State Control bits for trigger control */
  UINT4 iRadReq;    
  UINT4 iRfdSeqReq;
  UINT4 iCwTestReq;
  /* J7 RF Generator */
  UINT4 iPhCohoSelForce;
  UINT4 iPhCohoSelLevel;
  /* Control bits set in RVP */
  UINT4 iPulseRateInt0;
  UINT4 iPulseRateInt1;
  UINT4 iPulseRateInt2;
  /* Engineering Debug */
  UINT4 iForceUpdate;
  /* Extra expansion bits to 64 words */
  UINT4 iPad14x50[50];
};

#define ORDA88D_SETIO_MSK      0x80000000 /*   Make no change if bit is clear */
#define ORDA88D_SERIAL_BAUD    0x8
#define STRUCT_ORDA88DGETIO_U4_DEFINED 1
struct orda88dGetIO_u4 {
  /* Input status from pins */
  UINT4 iChanFail;
  UINT4 iCohoRefFail;
  UINT4 iPhModFail;
  UINT4 iOpFreqRefFl;
  /* radiation state status */
  UINT4 iRadiate;
  UINT4 iRfdTest;
  UINT4 iCwTest;
  /* currently unused bits */
  UINT4 iSpareStatBit1;
  UINT4 iSpareStatBit2;
  /* Version of the Panel */
  UINT4 iPanelVersion; 
  /* What IO mode the IFDR is in */
  UINT4 iIfdrIoMode;
  /* Extra expansion bits to 32 words */
  UINT4 iPad11x21[21];
};

// ORDA88D Diagnostic Force bits
#define ORDA88D_FORCE_ENA        0
#define ORDA88D_FORCE_TRIGFORCE  2
#define ORDA88D_FORCE_PHASEFORCE 3
#define ORDA88D_FORCE_LEDFORCE   4
#define ORDA88D_FORCE_PHASE_BLO  8
#define ORDA88D_FORCE_PHASE_BHI  14
#define ORDA88D_FORCE_TRIG_BLO   15
#define ORDA88D_FORCE_TRIG_BHI   24
#define ORDA88D_FORCE_RFGATE     15
#define ORDA88D_FORCE_RFPULSE    16
#define ORDA88D_FORCE_RFDRIVE    17
#define ORDA88D_FORCE_FILARESET  18
#define ORDA88D_FORCE_POSTCHRG   19
#define ORDA88D_FORCE_MODCHRG    20
#define ORDA88D_FORCE_MODDISCHRG 21
#define ORDA88D_FORCE_TRIGCHRG   22
#define ORDA88D_FORCE_PROTCMD    23
#define ORDA88D_FORCE_RVPTIME1   24
#define ORDA88D_FORCE_GOLED      25

#define ORDA88D_RVPTP_NONE          0  
#define ORDA88D_RVPTP_MAX           0


#endif /* #ifndef EMB_WR_MODULES_H */
