Logic Equation Timer Variables

Retriggerable Pulse Generator

(retrig)

Generates a TRUE pulse when a FALSE->TRUE (rising edge) transition is applied to its input.

Each rising edge continues to retrigger the output pulse, that is, a fresh pulse period is begun each time.

For example, if a rising edge were presented once per second to the timer t0_retrig_1.5, then the timer output would be a steady TRUE value. Since the 1.5-second timeout begins again once per second, the output pulse never actually ends.

retrig timers are useful for keeping track of whether any FALSE->TRUE transitions have occurred (perhaps irregularly) over a given period of time.

Change-Detecting Pulse Generator

(change)

This timer is like the retriggerable timer, except that either input edge causes the period to reset.

Use it if you require an output pulse in response to any change in measured conditions, for example, you could force radiate OFF briefly when the pulse width changes in either direction.

Single Pulse Generator

(single)

Generates a pulse similar to retrig, except that an active pulse is not retriggered by additional input transitions.

For example, if a rising edge were presented once per second to the timer t0_single_1.5, then the timer output would be a rectangular wave that is TRUE for 1.5 seconds and FALSE for 0.5 seconds. The 1.5-second TRUE pulse is first triggered by an input edge. One second later the timer is still active, so the next input edge is ignored. The pulse finally ends 1.5-seconds later, remains FALSE for 0.5 seconds, and then is triggered again by the next rising input edge.

The active-low application of single is also useful, as in the following two equations which prevent radiate from being switched back on within 60 seconds of it being switched off. Note that if a retrig timer were used here, then repeated attempts at radiating would keep resetting the 60-second interval even though the transmitter had never actually turned back on.

EQ00: t0_single_60 = !cradiate
EQ01: cradiate = cradiate & !t0_single_60

Delay Line Filter/Follower

(filter)

The output of this timer attempts to follow its input, but with filtering and delay effects added.

When a TRUE input is presented, an internal counter begins counting up until the timer period is reached. At that point the timer's output is set TRUE.

Likewise, a FALSE input causes the counter to decrement until reaching 0, at which point the timer's output is set FALSE. The net result is that the output follows the mean value of the input, and thus, a filter timer can be used to clean up a noisy logic signal, or combination of logic conditions.

Decisive-Grant, Indecisive-Wait

(fickle)

The fickle timer copies its input immediately to its output, unless the output has just changed recently (within the setup period of the timer), in which case the previous output level is held. Use this timer to cleanup requests for state changes so that "original" and "thoughtful" requests get honored (passed through) right away, but once honored, a given request can not be changed for some minimum amount of time.

The fickle timer can be used to protect against needless or damaging cycling of equipment that should not be turned On/Off rapidly. Air conditioner thermostats typically have such a timer to prevent the compressor from frequently stopping and restarting if the temperature dial is twirled up and down in an indecisive manner. After remaining in a stable state for a while, new requests are honored immediately (unlike the fickle timer which always introduces a delay). Once honored, that new setting once again persists for a little while.

Leading Edge Retard

(retard)

The output of this timer attempts to follow its input, except that rising input edges are delayed by the timer period, whereas falling input edges are passed through immediately. The result is that the leading edges of the input signal are delayed, but the falling edges are not.

A retard timer is useful when one wants to delay only the onset portion of a signal, for example, to holdoff transmitting for a few seconds after a radiate request has been made. It is also useful when filtering signals to remove short spurious TRUE inputs in which, contrasted with the filter timer, an instant-off effect is also required.

Trailing Edge Extend

(extend)

This timer is the counterpart to retard, in that the falling input edge is extended by the timer period and the rising input edge is passed immediately.

An extend timer forces a minimum time during which the timer output is TRUE in response to any (possibly momentary) TRUE input. It is useful for stretching a short input condition out to at least some minimum time, or for adding additional "hold time" to the end of a signal.

Note that the output of an extend timer is logically equivalent to the negation of the output of a retard timer whose input is also negated. Although these two timer classes are inverted-logic duals of each other, it is still conceptually useful to have both the "retard" and extend concepts. An analogy is that AND and OR are both useful logic concepts, even though an OR-gate is merely an AND-gate with inverted inputs and outputs.

Periodic Clock Oscillator

(clock)

Produces a free-running clock with specified period.

The length of the timer's TRUE interval (and the duty cycle) is adjustable.

The clock timers usually appear on the right side of equations, where they can supply any periodic input that the logic might require, for example, to make a light blink, or to perform a periodic reset. Their phase can also be resynchronized to the start of their TRUE output interval using a rising input edge.