Run Time FPGA Configuration

The Vaisala I/O-62 card is built around a 100-K Gate FPGA that drives the I/O signals on the 62-position connector and coordinates the PCI traffic.

The chips are SRAM-based, meaning that they are configured at run time. This allows the FPGA code to be automatically upgraded during each code release without needing to reprogram any parts.

The board's basic I/O services use up only 40 % of the complete FPGA. The leftover space makes it possible to add smart processing on the I/O-62 board to handle custom needs such as generating custom serial formats, data debouncing, and signal transition detection.