RVP10 product architecture

RVP10 consists of two hardware units:
  • IFDR10 Intermediate frequency digital receiver
  • RVP10SRV Signal processor computer
These devices interface via 1-Gigabit and 10-Gigabit Ethernet, and communicate via gRPC framework over the network layer.
Figure 1. RVP10 architecture

IFDR10 intermediate frequency digital receiver

IFDR10 intermediate frequency digital receiver (IFDR) provides receive, transmit, and IF detector functionality in a single, compact network-attached FGPA-based product able to perform tens of billions of multiply accumulate cycles per second.

The IFDR samples up to 4 receive channels and 2 burst channels of IF inputs and computes I and Q data from them. The I and Q data is transmitted over a 10-Gigabit Ethernet connection to the RVP10SRV signal processor for further processing into moments.

RVP10SRV signal processor computer

The RVP10SRV signal processor is a server class computer with a dual-processor multicore Xeon processor running Linux.

RVP10SRV, running RDA software, computes the radar data moments from the I and Q data provided by IFDR10. The moments incude Z,T,V, and W. The moments can be distributed internally on RVP10SRV, or externally to other computers running IRIS or third party software.