Configuring the IFDR10 clock subsystem

IFDR10 provides a programmable low jitter clock generator used in sampling the IF inputs and generating the IF outputs.

Clock generator
Source Description
Master clock source The IFDR10 ADCs and DACs are clocked by internal VCXO (Voltage Controlled Crystal Oscillator), which can be optionally locked to an external reference.
IF sampling frequency

The sampling clock frequency is fully programmable 50 ... 100 MHz with microhertz (μHz) resolution.

You can choose the clock frequency independently of the original reference clock frequency that produces it; they do not have to be small integer multiples of each other.

See Choosing A/D sample rate or Tx synthesis rate

The IFDR10 sampling clock is derived from the master clock source. The architecture minimizes jitter, while allowing full flexibility in selecting sampling frequencies 50 ... 100 MHz. The output clock runs at the same frequency as the sampling clock.

Clock jitter IF clock jitter is sub-picosecond allowing the system to maximize the benefits of the 16-bit A/D converters.
Clock generator concerns in a synchronous radar system
Concern Description
RVP10 generates the radar trigger

The IFDR10 trigger signals are inherently synchronous with the data sampling clock,

This is accomplished by a clock recovery PLL that provides on-board timing, which is identical to the sampling clock in the IFDR10. Since the IFDR10 sampling clock is asynchronous with the radar clocks, RVP10 trigger outputs are similarly asynchronous. The result is that each transmitted pulse envelope is triggered independently of the COHO phase. The transmitted pulse is still synchronous, but the precise alignment of the amplitude modulated envelope varies.

In almost all cases, the exact placement of the transmitter’s amplitude envelope does not affect the overall system stability, nor the ability of RVP10 to reject ground clutter and to process multi-mode return signals. For this reason, a synchronous radar system, which is triggered using RVP10 triggers, still performs optimally using the standard digital COHO locking techniques. In spite of this, some system designers may still prefer that the amplitude envelope be locked to the COHO.

RVP10 Receives the Existing Radar Trigger

When an external trigger is supplied to RVP10, the processor synchronizes its internal range bin selection circuitry to that external trigger. The placement of the range bins themselves, however, is always synchronous with the IFDR10 selectable sampling clock. The result is that 27.8 nanoseconds of jitter is introduced in the placement of RVP10 range bins relative to the transmitted pulse.

The effect of this synchronization jitter is that targets appear fluctuate in range by approximately 4.2 m. Although this is small, relative to the range bin spacing, and does not affect the range accuracy of the data, the effect on overall system stability is more severe. Using both numerical modeling and field measurements, we have found that sub-clutter visibility of a μsec pulse may be limited to approximately 43 dB as a result of this 27.8 nanoseconds range jitter. This falls quite short of the usual expectations of a synchronous radar system in which clutter rejection of 55 ... 60 dB should be attainable.

The solution to these concerns is to provide a way for the IFDR10 internal sampling clock to be phase-locked to the radar system. If RVP10 provides the radar triggers, then those triggers become synchronous with the radar COHO. If RVP10 receives an external trigger, then its range bin clock is synchronous with that external trigger, and there is no synchronization jitter in the range bins.

The IFDR10 can lock its sampling clock to an external system clock reference through an SMA input. This results in an RVP10 that is fully synchronous with the existing radar timing.