V and Vz – View card and system status

The V command displays internal diagnostics.

This information is for inspection only, and cannot be changed from the TTY.

If invoked as Vz, the counters are cleared, so that subsequent V commands show what has accumulated since the last Vz.

The view listing displays:

Configuration and Internal Status
--------------------------------
RVP10 Digital IF Signal Processor V13.1(Pol) IRIS–10.0.0

The displayed version of RVP10 code was the last to write into the non-volatile RAM. It is printed only if that last version was different from the version that is currently running.

Settings were last saved using V12.3

Then, information about when the RVP10 was started, current system time, and implicitly, the uptime.

RVP10 started at: 13:07:33 3 JUN 2022
Current time is: 13:14:03 3 JUN 2022

Then information about the processor and the Intel libraries used for RVP10 processing.

CPU–Type: Pentium(R) 4 Hyperthreaded
IPP–Library: libippsw7.so v4.0 4.0.19.77

If errors were detected by the startup diagnostics, then an error bitmask is shown. PASS indicates that no errors were detected.

Diagnostics: PASS

The Process and Threads list displays RVP10 processes and their related priority. All RVP10 processes and threads should run under RealTimeRR policy to guarantee adequate attention from the processors.

Processes and Threads:
RVP10Proc-0  –   PID:6917Priority:10 Policy:RealTimeRR 
RVP10Proc-1  –   PID:6918  Priority:10 Policy:RealTimeRR 
  Chat/Plot   –   PID:6909Priority:10 Policy:RealTimeRR 
  Watchdog    –   PID:6909Priority:10 Policy:RealTimeRR 
  Burst/AFC   –   PID:6909Priority:10 Policy:RealTimeRR 
  HostCmds    –   PID:6909Priority:11 Policy:RealTimeRR 
  Angles      –   PID:6909Priority:12 Policy:RealTimeRR    
  RtCtrl-0    –   PID:6909Priority:12 Policy:RealTimeRR 
  RtCtrl-1    –   PID:6909Priority:12 Policy:RealTimeRR 
  IQ-Data     –   PID:6909  Priority:13 Policy:RealTimeRR

This section provides RVP10 developers with information about code resources.

Shared library build dates:
RVP10/Main/Core:MonApr216:01:12EDT2022
RVP10/Main/Open:MonApr216:01:13EDT2022
RVP10/Main/Site:MonApr216:01:12EDT2022
RVP10/Proc/Core:MonApr216:01:14EDT2022
RVP10/Proc/Open:MonApr216:01:16EDT2022
RVP10/Proc/Site:MonApr216:01:14EDT2022

This line shows the status of optional GPS time synchronization of the RVP10 triggers and range bins.

GPS:Inused

AFC indicates the level and status of the AFC voltage at the IFDR module. The number is the present output level in D-Units ranging -100 … +100. The shorter % symbol is used since percentage units correspond in a natural way to the D-Units.

Burst Pwr indicates the mean power within the full window of burst samples. DC offsets in the A/D converter do not affect the computation of the power, that is, the value shown truly represents the waveform’s (Signal+Noise) energy. Freq indicates the mean frequency of the burst, derived from a fourth order correlation model. See chapter V and Vz - View card and system status.

AFC:0.00% (Disabled), Burst Pwr:–48.6 dBm, Freq:30.000 MHz

AFC :0.00 % (Disabled), Burst Pwr :–48.6 dBm , Freq:30.000 MHz

This line shows the case temperature and FPGA chip core temperature, both in °C and °F.

IFD Temperature – Chassis: 37C (99F), FPGA: 38C (100F) )

This line shows the presently operating receiver mode.

Receiver mode: 0 (Standard single channel)

TrigRAM using 4.8% of 588–KBytes, TrigCount:8777651