Data acquisition and convertors

Six IF channels are present within the IFDR10. These consist of identical receiver paths with 16-bit analog-to-digital convertors (ADC) that sample up to 240 MHz. The actual sampling frequency is user-controllable, 190 ... 240 MHz. These six channels allow an input frequency of 10 ... 120 MHz. The ADCs are transformer coupled with an ideal impedence of 50 ohms. In reality there is slight difference in impedence values depending on the IF center frequency. However, this design introduces virtually no noise, which is advantageous.

Uncertainty in high-speed ADCs may be introduced if the sampling gets confined to a small region, especially with low signal-to-noise ratio. In such a case the integral non-linearity of the ADC may cause a few tenths of a dB difference in power measurement when the ADCs are toggling a small number of bits. This becomes extremely relevant in ZDR, as different offsets will occur across the dynamic range of the receiver. A dithering signal is introduced in front of the ADCs at low frequency to ensure that all bits are being toggled, even when we are only interested in a small region. This avoids the introduction of non-linear response, keeping consistent measured gains between multiple ADCs over the full dynamic range.

IFDR10 uses two RF digital-to-analog convertors (DAC) capable of rates up to 6.2 GSa/s. Each DAC device has two separate data paths, each receiving one complex baseband data stream from the FPGA. Currently, one of these paths is used for producing a low frequency dithering signal described in the previous paragraph. Thus, this allows up to three transmit waveform designs to be used in parallel.