Timing / clocks

IFDR10 clocking and synchronization between the analog-to-digital and digital-to-analog data convertors, FPGA logic devices, and real-time embedded Linux threads are based upon the JESD204B standard. This is the first use of a standardized interface between the data convertors (ADCs and DACs) and logic devices.

JED204B allows IFDR10 to achieve deterministic latency across every serial link, from boot to boot. This enables synchronous sampling, multi-channel phase alignment, and gain control between the six ADCs, 4 TXDACs, and the FPGA within the system. In the first release, IFDR10 supports phase locking to a 10-MHz external reference clock.