IFDR10: IF to I and Q processing

The conversion of IF ADC samples to I and Q within the IFDR10 consists of the decimation stage, which combines the moving average filter, and the down-sampling. The moving average filter is also known as the convolution completed by a finite impulse response (FIR) filter. Depending on the selected configuration, the FIR filter is either a bandpass filter or a matching filter. In either case, the FIR filter is smoothing the signal, and as a result, most of the samples in the filtered data are redundant and can be dropped. The stage that drops the samples is called down-sampling. The IFDR10 has plenty of FPGA resources to perform these actions in parallel for the 6 receive channels.

The direct implementation of a moving average filter and then down-sampling is extremely inefficient because for each stage of decimation only one filter is used. Therefore, a polyphase filter is implemented, which combines the filtering and down-sampling into one step. The IFDR10 FPGA performs the initial processing of the raw IF digital data generated by the ADCs and output I and Q data values to the RVP10SRV host computer. The frequency, phase, and amplitude of the burst pulse from every transmitter are also measured.